Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12346264 | Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices | Bret L. Toll, Benjamin Crawford Chaffin, George Van Horn Leming, III | 2025-07-01 |
| 12175243 | Hardware micro-fused memory operations | Jason Anthony Bessette, Sean P. Mirkes, Jacob Daniel Morgan, John Saint Tran | 2024-12-24 |
| 11822487 | Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer | George Van Horn Leming, III, John G. Favor, Stephan Jourdan, Bret L. Toll | 2023-11-21 |
| 11586537 | Method, apparatus, and system for run-time checking of memory tags in a processor-based system | Benjamin Crawford Chaffin, Bret L. Toll, Nagi Aboulenein | 2023-02-21 |
| 11386016 | Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer | George Van Horn Leming, III, John G. Favor, Stephan Jourdan, Bret L. Toll | 2022-07-12 |
| 10860319 | Apparatus and method for an early page predictor for a memory paging subsystem | Mark Dechene, Manjunath Shevgoor, Faruk Guvenilir, Zhongying Zhang | 2020-12-08 |
| D902304 | Globe with stand | Chieh-Yu Lin | 2020-11-17 |
| 10348600 | Controlling flow rates of traffic among endpoints in a network | — | 2019-07-09 |
| 9270412 | Permute codes, iterative ensembles, graphical hash codes, and puncturing optimization | Hari Balakrishnan, Devavrat Shah | 2016-02-23 |
| 9143175 | Rateless and rated coding using spinal codes | Devavrat Shah, Hari Balakrishnan | 2015-09-22 |
| 8724715 | Rateless and rated coding using spinal codes | Devavrat Shah, Hari Balakrishnan | 2014-05-13 |
| 7857689 | Air handling system with self balancing air entrance door | — | 2010-12-28 |