JR

Jens K. Ramsey

CC Compaq Computer: 16 patents #32 of 1,604Top 2%
HP HP: 1 patents #8,774 of 16,619Top 55%
Overall (All Time): #279,560 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7120758 Technique for improving processor performance Phillip M. Jones, Robert A. Lester, William J. Walker, John E. Larson, James R. Andre +1 more 2006-10-10
6209067 Computer system controller and method with processor write posting hold off on PCI master memory request Michael J. Collins, Michael Moriarty, John E. Larson 2001-03-27
6041401 Computer system that places a cache memory into low power mode in response to special bus cycles executed on the bus Jeffrey C. Stevens, Michael E. Tubbs, Charles J. Stancil 2000-03-21
5938739 Memory controller including write posting queues, bus read control logic, and a data contents counter Michael J. Collins, Gary W. Thome, Michael Moriarty, John E. Larson 1999-08-17
5895490 Computer system cache performance on write allocation cycles by immediately setting the modified bit true — 1999-04-20
5872939 Bus arbitration Alan L. Goodrum, Paul R. Culley 1999-02-16
5835948 Single bank, multiple way cache memory Sompong Paul Olarig, Michael J. Collins 1998-11-10
5822571 Synchronizing data between devices Alan L. Goodrum, Paul R. Culley, Joseph P. Miller 1998-10-13
5822756 Microprocessor cache memory way prediction based on the way of a previous memory read Gary W. Thome 1998-10-13
5813022 Circuit for placing a cache memory into low power mode in response to special bus cycles executed on the bus Jeffrey C. Stevens, Michael E. Tubbs, Charles J. Stancil 1998-09-22
5781925 Method of preventing cache corruption during microprocessor pipelined burst operations John E. Larson, Jeffrey C. Stevens, Michael J. Collins 1998-07-14
5699550 Computer system cache performance on write allocation cycles by immediately setting the modified bit true — 1997-12-16
5640532 Microprocessor cache memory way prediction based on the way of previous memory read Gary W. Thome 1997-06-17
5634073 System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation Michael J. Collins, Gary W. Thome, Michael Moriarty, John E. Larson 1997-05-27
5446863 Cache snoop latency prevention apparatus Jeffrey C. Stevens, Randy M. Bonella, Philip C. Kelly 1995-08-29
5426765 Multiprocessor cache abitration Jeffrey C. Stevens, Mike Jackson, Roger E. Tipley, Sompong Paul Olarig, Philip C. Kelly 1995-06-20
5325503 Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line Jeffrey C. Stevens, Randy M. Bonella, Philip C. Kelly 1994-06-28