Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5652856 | Memory controller having all DRAM address and control singals provided synchronously from a single device | Paul Santeler | 1997-07-29 |
| 5651130 | Memory controller that dynamically predicts page misses | Lee B. Hinkle, Paul Santeler, David R. Wooten, Jr., John A. Landry | 1997-07-22 |
| 5640532 | Microprocessor cache memory way prediction based on the way of previous memory read | Jens K. Ramsey | 1997-06-17 |
| 5634073 | System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation | Michael J. Collins, Michael Moriarty, Jens K. Ramsey, John E. Larson | 1997-05-27 |
| 5634112 | Memory controller having precharge prediction based on processor and PCI bus cycles | Michael Moriarty, John E. Larson | 1997-05-27 |
| 5604884 | Burst SRAMS for use with a high speed clock | Michael J. Collins | 1997-02-18 |
| 5596741 | Computer system which overrides write protection status during execution in system management mode | — | 1997-01-21 |
| 5586286 | Memory controller having flip-flops for synchronously generating DRAM address and control signals from a single chip | Paul Santeler | 1996-12-17 |
| 5581727 | Hierarchical cache system flushing scheme based on monitoring and decoding processor bus cycles for flush/clear sequence control | Michael J. Collins | 1996-12-03 |
| 5579512 | Systempro emulation in a symmetric multiprocessing computer system | Alan L. Goodrum | 1996-11-26 |
| 5537555 | Fully pipelined and highly concurrent memory controller | John A. Landry, Paul Santeler, Randy M. Bonella, Michael J. Collins | 1996-07-16 |
| 5524235 | System for arbitrating access to memory with dynamic priority assignment | John E. Larson, Michael Moriarty, Michael J. Collins | 1996-06-04 |
| 5509138 | Method for determining speeds of memory modules | Christine G. Cash | 1996-04-16 |
| 5509139 | Circuit for disabling an address masking control signal using OR gate when a microprocessor is in a system management mode | Basem Abu Ayash | 1996-04-16 |
| 5475829 | Computer system which overrides write protection status during execution in system management mode | — | 1995-12-12 |
| 5454081 | Expansion bus type determination apparatus | — | 1995-09-26 |
| 5440751 | Burst data transfer to single cycle data transfer conversion and strobe signal conversion | Paul Santeler | 1995-08-08 |
| 5423021 | Auxiliary control signal decode using high performance address lines | Harry Roger | 1995-06-06 |
| 5408636 | System for flushing first and second caches upon detection of a write operation to write protected areas | Paul Santeler, Roger E. Tipley | 1995-04-18 |
| 5404559 | Apparatus for asserting an end of cycle signal to a processor bus in a computer system if a special cycle is detected on the processor bus without taking action on the special cycle | Randy M. Bonella, John A. Landry | 1995-04-04 |
| 5353423 | Memory controller for use with write-back cache system and multiple bus masters coupled to multiple buses | Mustafa A. Hamid | 1994-10-04 |
| 5325535 | Lock signal extension and interruption apparatus | Paul Santeler | 1994-06-28 |
| 5289584 | Memory system with FIFO data input | Mustafa A. Hamid | 1994-02-22 |
| 5210847 | Noncacheable address random access memory | James H. Nuckols, Paul R. Culley, Gary Brasher | 1993-05-11 |