Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11360782 | Processors to configure subsystems while other processors are held in reset | Naysen J. Robertson, Theodore F. Emerson | 2022-06-14 |
| 11138140 | Configuring first subsystem with a master processor and a second subsystem with a slave processor | Naysen J. Robertson, Theodore F. Emerson | 2021-10-05 |
| 10404244 | Adjustments of output clocks | Christopher M. Wesneski, Theodore F. Emerson | 2019-09-03 |
| 10372400 | Video management for compute nodes | Theodore F. Emerson, David F. Heinrich | 2019-08-06 |
| 8174977 | End-to-end flow control in a network | Paul V. Brownell, David L. Matthews, James Xuan Dinh, Hubert E. Brinkmann, Dwight D. Riley +1 more | 2012-05-08 |
| 7876759 | Quality of service with control flow packet filtering | Hahn Norden, Hubert E. Brinkmann, Paul V. Brownell, James Xuan Dinh, David L. Matthews +1 more | 2011-01-25 |
| 6961800 | Method for improving processor performance | Robert A. Lester, Jim Blocker, John E. Larson, Phillip M. Jones, Paul B. Rawlins | 2005-11-01 |
| 6829665 | Next snoop predictor in a host controller | Phillip M. Jones, Paul B. Rawlins | 2004-12-07 |
| 6505260 | Computer system with adaptive memory arbitration scheme | C. Kevin Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +2 more | 2003-01-07 |
| 6356972 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2002-03-12 |
| 6286083 | Computer system with adaptive memory arbitration scheme | Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo, Jeffrey C. Stevens +2 more | 2001-09-04 |
| 6279065 | Computer system with improved memory access | Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo, C. Kevin Coffee +1 more | 2001-08-21 |
| 6275885 | System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache | Michael J. Collins, John E. Larson, Robert A. Lester | 2001-08-14 |
| 6272651 | System and method for improving processor read latency in a system employing error checking and correction | Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-08-07 |
| 6249847 | Computer system with synchronous memory arbiter that permits asynchronous memory requests | Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo, Michael J. Collins | 2001-06-19 |
| 6247102 | Computer system employing memory controller and bridge interface permitting concurrent operation | Jerome J. Johnson, Phillip M. Jones, Robert A. Lester, Gary J. Piccirillo, Jeffrey C. Stevens +3 more | 2001-06-12 |
| 6216190 | System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus | Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-04-10 |
| 6209052 | System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter | Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-27 |
| 6202101 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-13 |
| 6199118 | System and method for aligning an initial cache line of data read from an input/output device by a central processing unit | Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-06 |
| 6160562 | System and method for aligning an initial cache line of data read from local memory by an input/output device | Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2000-12-12 |
| 5905509 | Accelerated Graphics Port two level Gart cache having distributed first level caches | Phillip M. Jones, Robert A. Lester | 1999-05-18 |