Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12120516 | Dynamically enabling a security feature of a wireless communication device based on environmental context | Melanie A. King, Friedrich Bollmann, Divya Ramamoorthy, David Weygandt | 2024-10-15 |
| 11653193 | Communication system and method for controlling access to portable radio public safety service applications | Melanie A. King, Friedrich Bollmann, Divya Ramamoorthy, David Weygandt | 2023-05-16 |
| 10491235 | Devices and methods for multi-mode sample generation | Charles R. Ruelke | 2019-11-26 |
| 7376777 | Performing an N-bit write access to an M×N-bit-only peripheral | Eytan Hartung | 2008-05-20 |
| 6356972 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Kenneth T. Chin, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2002-03-12 |
| 6272651 | System and method for improving processor read latency in a system employing error checking and correction | Kenneth T. Chin, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-08-07 |
| 6216190 | System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus | Kenneth T. Chin, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-04-10 |
| 6209052 | System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter | Kenneth T. Chin, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-27 |
| 6202101 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Kenneth T. Chin, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-13 |
| 6199118 | System and method for aligning an initial cache line of data read from an input/output device by a central processing unit | Kenneth T. Chin, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-06 |
| 6160562 | System and method for aligning an initial cache line of data read from local memory by an input/output device | Kenneth T. Chin, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones, Robert A. Lester +1 more | 2000-12-12 |