Issued Patents All Time
Showing 26–30 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6209052 | System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-27 |
| 6202101 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-13 |
| 6199118 | System and method for aligning an initial cache line of data read from an input/output device by a central processing unit | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Phillip M. Jones, Robert A. Lester +1 more | 2001-03-06 |
| 6160562 | System and method for aligning an initial cache line of data read from local memory by an input/output device | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Phillip M. Jones, Robert A. Lester +1 more | 2000-12-12 |
| 5949436 | Accelerated graphics port multiple entry gart cache allocation system and method | Ronald T. Horan, Phillip M. Jones, Gregory N. Santos, Robert A. Lester, Michael J. Collins | 1999-09-07 |