Issued Patents All Time
Showing 1–25 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11720287 | System and method for memory management | — | 2023-08-08 |
| 11663149 | System and method for memory management | Thomas J. Shepherd, Davika Raghu | 2023-05-30 |
| 10956342 | Variable channel multi-controller memory system | Jerome J. Johnson, Landon Laws, Anne Hughes | 2021-03-23 |
| 10769013 | Caching error checking data for memory having inline storage configurations | Landon Laws, Carl Nels Olson, Thomas J. Shepherd | 2020-09-08 |
| 10719058 | System and method for memory control having selectively distributed power-on processing | Jerome J. Johnson, Sreenivasan Kandagatla | 2020-07-21 |
| 10642684 | Memory command interleaving | Anne Hughes, Thomas J. Shepherd, Carl Nels Olson | 2020-05-05 |
| 10642538 | Multi-channel memory interface | Jeffrey Earl, Anne Hughes | 2020-05-05 |
| 10579470 | Address failure detection for memory devices having inline storage configurations | Carl Nels Olson | 2020-03-03 |
| 10534565 | Programmable, area-optimized bank group rotation system for memory devices | Bikram Banerjee, Anne Hughes | 2020-01-14 |
| 10446215 | System and method for adaptively optimized refresh of memory | Anne Hughes, Devika Raghu | 2019-10-15 |
| 10303543 | System and method for memory control having address integrity protection for error-protected data words of memory transactions | — | 2019-05-28 |
| 10282250 | Apparatus and method for a coherent, efficient, and configurable cyclic redundancy check retry implementation for synchronous dynamic random access memory | Bikram Banerjee, Anne Hughes | 2019-05-07 |
| 10275306 | System and method for memory control having adaptively split addressing of error-protected data words in memory transactions for inline storage configurations | Carl Nels Olson, Jerome J. Johnson, Thomas J. Shepherd | 2019-04-30 |
| 10037246 | System and method for memory control having self writeback of data stored in memory with correctable error | Landon Laws, Anne Hughes | 2018-07-31 |
| 8429438 | Method and apparatus for transferring data between asynchronous clock domains | Anne Espinoza | 2013-04-23 |
| 8098535 | Method and apparatus for gate training in memory interfaces | Anne Espinoza | 2012-01-17 |
| 7952945 | Method and apparatus for determining write leveling delay for memory interfaces | Anne Espinoza | 2011-05-31 |
| 7353328 | Memory testing | Thomas J. Bonola, Jerry Johnson | 2008-04-01 |
| 7320086 | Error indication in a raid memory system | Tim Majni, Gary J. Piccirillo, Robert A. Lester, John E. Larson, Jerome J. Johnson +8 more | 2008-01-15 |
| 7194577 | Memory latency and bandwidth optimizations | Jerome J. Johnson, Benjamin H. Clark, Gary J. Piccirillo | 2007-03-20 |
| 7116241 | Removable memory cartridge system for use with a server or other processor-based device | Christian Post, George D. Megason, Brett D. Roscoe, Paul Santeler, John E. Larson +6 more | 2006-10-03 |
| 7044770 | Technique for identifying multiple circuit components | John E. Larson | 2006-05-16 |
| 7028213 | Error indication in a raid memory system | Tim Majni, Gary J. Piccirillo, Robert A. Lester, John E. Larson, Jerome J. Johnson +8 more | 2006-04-11 |
| 7010652 | Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency | Gary J. Piccirillo, Robert A. Lester, John E. Larson, Jerome J. Johnson, Benjamin H. Clark | 2006-03-07 |
| 6981095 | Hot replace power control sequence logic | Jerome J. Johnson, Robert A. Lester, Gary J. Piccirillo, John E. Larson, Christian Post +3 more | 2005-12-27 |