Issued Patents All Time
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10257208 | Method and system for using a network analysis system to verify content on a website | Victor Bennett, Shrish Agrawal, Niels Provos, Jayesh Sharma, Gokul Rajaram | 2019-04-09 |
| 8762280 | Method and system for using a network analysis system to verify content on a website | Victor Bennett, Shrish Agrawal, Niels Provos, Jayesh Sharma, Gokul Rajaram | 2014-06-24 |
| 7523016 | Detecting anomalies | Razvan Surdulescu | 2009-04-21 |
| 7502895 | Techniques for reducing castouts in a snoop filter | Phillip M. Jones | 2009-03-10 |
| 7467131 | Method and system for query data caching and optimization in a search engine system | Fay Wen Chang, Deborah Anne Wallach | 2008-12-16 |
| 7389389 | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system | Luiz Andre Barroso, Robert Stets, Mosur K. Ravishankar, Andreas Nowatzyk | 2008-06-17 |
| 7254580 | System and method for selectively searching partitions of a database | Fay Wen Chang, Deborah Anne Wallach, Sanjay Ghemawat, Jeffrey Adgate Dean | 2007-08-07 |
| 7174346 | System and method for searching an extended database | Fay Wen Chang, Deborah Anne Wallach, Sanjay Ghemawat, Jeffrey Adgate Dean | 2007-02-06 |
| 7152191 | Fault containment and error recovery in a scalable multiprocessor | Richard E. Kessler, Peter J. Bannon, Thukalan V. Verghese | 2006-12-19 |
| 6988170 | Scalable architecture based on single-chip multiprocessing | Luiz Andre Barroso, Andreas Nowatzyk | 2006-01-17 |
| 6925537 | Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants | Luiz Andre Barroso, Andreas Nowatzyk, Mosur K. Ravishankar, Robert Stets | 2005-08-02 |
| 6918015 | Scalable directory based cache coherence protocol | Richard E. Kessler, David Asher | 2005-07-12 |
| 6912624 | Method and system for exclusive two-level caching in a chip-multiprocessor | Luiz Andre Barroso, Andreas Nowatzyk | 2005-06-28 |
| 6751720 | Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy | Luiz Andre Barroso, Andreas Nowatzyk, Robert Stets, Mosur K. Ravishankar | 2004-06-15 |
| 6751710 | Scalable multiprocessor system and cache coherence method | Luiz Andre Barroso, Mosur K. Ravishankar, Robert Stets, Daniel J. Scales | 2004-06-15 |
| 6748498 | Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector | Luiz Andre Barroso, Mosur K. Ravishankar, Robert Stets, Daniel J. Scales | 2004-06-08 |
| 6738868 | System for minimizing directory information in scalable multiprocessor systems with logically independent input/output nodes | Luiz Andre Barroso, Daniel J. Scales | 2004-05-18 |
| 6725334 | Method and system for exclusive two-level caching in a chip-multiprocessor | Luiz Andre Barroso, Andreas Nowatzyk | 2004-04-20 |
| 6725343 | System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system | Luiz Andre Barroso, Andreas Nowatzyk | 2004-04-20 |
| 6697919 | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system | Luiz Andre Barroso, Robert Stets, Mosur K. Ravishankar, Andreas Nowatzyk | 2004-02-24 |
| 6678840 | Fault containment and error recovery in a scalable multiprocessor | Richard E. Kessler, Peter J. Bannon, Thukalan V. Verghese | 2004-01-13 |
| 6675265 | Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants | Luiz Andre Barroso, Andreas Nowatzyk, Mosur K. Ravishankar, Robert Stets | 2004-01-06 |
| 6668308 | Scalable architecture based on single-chip multiprocessing | Luiz Andre Barroso, Andreas Nowatzyk | 2003-12-23 |
| 6640287 | Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests | Luiz Andre Barroso, Mosur K. Ravishankar, Robert Stets, Daniel J. Scales | 2003-10-28 |
| 6636949 | System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing | Luiz Andre Barroso, Andreas Nowatzyk, Robert Stets, Mosur K. Ravishankar | 2003-10-21 |