Issued Patents All Time
Showing 26–39 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6633960 | Scalable directory based cache coherence protocol | Richard E. Kessler, David Asher | 2003-10-14 |
| 6622218 | Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system | Luiz Andre Barroso, Mosur K. Ravishankar, Robert Stets | 2003-09-16 |
| 6622217 | Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system | Luiz Andre Barroso, Mosur K. Ravishankar, Robert Stets, Andreas Nowatzyk | 2003-09-16 |
| 6412056 | Extended translation lookaside buffer with fine-grain state bits | Daniel J. Scales | 2002-06-25 |
| 6286090 | Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches | Simon C. Steely, Jr., Madhumitra Sharma, Stephen R. Van Doren | 2001-09-04 |
| 6209065 | Mechanism for optimizing generation of commit-signals in a distributed shared-memory system | Stephen R. Van Doren, Simon C. Steely, Jr., Madhumitra Sharma | 2001-03-27 |
| 6108737 | Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system | Madhumitra Sharma, Stephen R. Van Doren, Simon C. Steely, Jr. | 2000-08-22 |
| 6101420 | Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories | Stephen R. VanDoren, Simon C. Steely, Jr., Madhumitra Sharma | 2000-08-08 |
| 6088771 | Mechanism for reducing latency of memory barrier operations on a multiprocessor system | Simon C. Steely, Jr., Madhumitra Sharma, Stephen R. Van Doren | 2000-07-11 |
| 6085263 | Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor | Madhumitra Sharma, Chester Pawlowski, Stephen R. Van Doren, Simon C. Steely, Jr. | 2000-07-04 |
| 6055605 | Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches | Madhumitra Sharma, Simon C. Steely, Jr., Stephen R. Van Doren | 2000-04-25 |
| 5950228 | Variable-grained memory sharing for clusters of symmetric multi-processors using private and shared state tables | Daniel J. Scales, Anshu Aggarwal | 1999-09-07 |
| 5933598 | Method for sharing variable-grained memory of workstations by sending particular block including line and size of the block to exchange shared data structures | Daniel J. Scales | 1999-08-03 |
| 5787480 | Lock-up free data sharing | Daniel J. Scales | 1998-07-28 |