Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8744856 | Computer implemented system and method and computer program product for evaluating pronunciation of phonemes in a language | — | 2014-06-03 |
| 7389389 | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system | Kourosh Gharachorloo, Luiz Andre Barroso, Robert Stets, Andreas Nowatzyk | 2008-06-17 |
| 6925537 | Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants | Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Robert Stets | 2005-08-02 |
| 6751710 | Scalable multiprocessor system and cache coherence method | Kourosh Gharachorloo, Luiz Andre Barroso, Robert Stets, Daniel J. Scales | 2004-06-15 |
| 6751720 | Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy | Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Robert Stets | 2004-06-15 |
| 6748498 | Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector | Kourosh Gharachorloo, Luiz Andre Barroso, Robert Stets, Daniel J. Scales | 2004-06-08 |
| 6697919 | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system | Kourosh Gharachorloo, Luiz Andre Barroso, Robert Stets, Andreas Nowatzyk | 2004-02-24 |
| 6675265 | Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants | Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Robert Stets | 2004-01-06 |
| 6640287 | Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests | Kourosh Gharachorloo, Luiz Andre Barroso, Robert Stets, Daniel J. Scales | 2003-10-28 |
| 6636949 | System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing | Luiz Andre Barroso, Kourosh Gharachorloo, Andreas Nowatzyk, Robert Stets | 2003-10-21 |
| 6622217 | Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system | Kourosh Gharachorloo, Luiz Andre Barroso, Robert Stets, Andreas Nowatzyk | 2003-09-16 |
| 6622218 | Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system | Kourosh Gharachorloo, Luiz Andre Barroso, Robert Stets | 2003-09-16 |