Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11017130 | Data center design | Andrew B. Carlson, Jimmy Clidaras, William Hamburgen, Wolf-Dietrich Weber, Xiaobo Fan | 2021-05-25 |
| 10558768 | Computer and data center load determination | Wolf-Dietrich Weber, Xiaobo Fan | 2020-02-11 |
| 10339227 | Data center design | Andrew B. Carlson, Jimmy Clidaras, William Hamburgen, Wolf-Dietrich Weber, Xiaobo Fan | 2019-07-02 |
| 10127076 | Low latency thread context caching | James Laudon, Michael Marty | 2018-11-13 |
| 9946815 | Computer and data center load determination | Wolf-Dietrich Weber, Xiaobo Fan | 2018-04-17 |
| 9779058 | Modulating processsor core operations | — | 2017-10-03 |
| 9563216 | Managing power between data center loads | Christopher G. Malone, Taliver Heath, Nathaniel Edward Pettis, Stephanie Hua Taylor, Michael C. Ryan | 2017-02-07 |
| 9384036 | Low latency thread context caching | James Laudon, Michael Marty | 2016-07-05 |
| 9250999 | Non-volatile random access memory in computer primary memory | — | 2016-02-02 |
| 9218310 | Shared input/output (I/O) unit | James Laudon | 2015-12-22 |
| 8949646 | Data center load monitoring for utilizing an access power amount based on a projected peak power usage and a monitored power usage | Wolf-Dietrich Weber, Xiaobo Fan | 2015-02-03 |
| 8700929 | Load control in a data center | Wolf-Dietrich Weber, Xiaobo Fan | 2014-04-15 |
| 8645722 | Computer and data center load determination | Wolf-Dietrich Weber, Xiaobo Fan | 2014-02-04 |
| 8621248 | Load control in a data center | Wolf-Dietrich Weber, Xiaobo Fan | 2013-12-31 |
| 8601287 | Computer and data center load determination | Wolf-Dietrich Weber, Xiaobo Fan | 2013-12-03 |
| 8595515 | Powering a data center | Wolf-Dietrich Weber, Xiaobo Fan | 2013-11-26 |
| 7934131 | Server farm diagnostic and status system | Eduardo Pinheiro, Andrew Tibbits, Wolf-Dietrich Weber | 2011-04-26 |
| 7389389 | System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system | Kourosh Gharachorloo, Robert Stets, Mosur K. Ravishankar, Andreas Nowatzyk | 2008-06-17 |
| 7386616 | System and method for providing load balanced processing | Monika H. Henzinger, Deborah Anne Wallach, Jeffrey Adgate Dean, Sanjay Ghemawat, Benjamin Thomas Smith | 2008-06-10 |
| 6988170 | Scalable architecture based on single-chip multiprocessing | Kourosh Gharachorloo, Andreas Nowatzyk | 2006-01-17 |
| 6925537 | Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants | Kourosh Gharachorloo, Andreas Nowatzyk, Mosur K. Ravishankar, Robert Stets | 2005-08-02 |
| 6912624 | Method and system for exclusive two-level caching in a chip-multiprocessor | Kourosh Gharachorloo, Andreas Nowatzyk | 2005-06-28 |
| 6751720 | Method and system for detecting and resolving virtual address synonyms in a two-level cache hierarchy | Kourosh Gharachorloo, Andreas Nowatzyk, Robert Stets, Mosur K. Ravishankar | 2004-06-15 |
| 6751710 | Scalable multiprocessor system and cache coherence method | Kourosh Gharachorloo, Mosur K. Ravishankar, Robert Stets, Daniel J. Scales | 2004-06-15 |
| 6748498 | Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector | Kourosh Gharachorloo, Mosur K. Ravishankar, Robert Stets, Daniel J. Scales | 2004-06-08 |