LB

Luiz Andre Barroso

HP HP: 17 patents #745 of 16,619Top 5%
Google: 14 patents #1,679 of 22,993Top 8%
EX Exaflop: 4 patents #10 of 30Top 35%
📍 Los Altos Hills, CA: #90 of 812 inventorsTop 15%
🗺 California: #13,801 of 386,348 inventorsTop 4%
Overall (All Time): #98,318 of 4,157,543Top 3%
35
Patents All Time

Issued Patents All Time

Showing 26–35 of 35 patents

Patent #TitleCo-InventorsDate
6738868 System for minimizing directory information in scalable multiprocessor systems with logically independent input/output nodes Kourosh Gharachorloo, Daniel J. Scales 2004-05-18
6725343 System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system Kourosh Gharachorloo, Andreas Nowatzyk 2004-04-20
6725334 Method and system for exclusive two-level caching in a chip-multiprocessor Kourosh Gharachorloo, Andreas Nowatzyk 2004-04-20
6697919 System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system Kourosh Gharachorloo, Robert Stets, Mosur K. Ravishankar, Andreas Nowatzyk 2004-02-24
6675265 Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants Kourosh Gharachorloo, Andreas Nowatzyk, Mosur K. Ravishankar, Robert Stets 2004-01-06
6668308 Scalable architecture based on single-chip multiprocessing Kourosh Gharachorloo, Andreas Nowatzyk 2003-12-23
6640287 Scalable multiprocessor system and cache coherence method incorporating invalid-to-dirty requests Kourosh Gharachorloo, Mosur K. Ravishankar, Robert Stets, Daniel J. Scales 2003-10-28
6636949 System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing Kourosh Gharachorloo, Andreas Nowatzyk, Robert Stets, Mosur K. Ravishankar 2003-10-21
6622218 Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system Kourosh Gharachorloo, Mosur K. Ravishankar, Robert Stets 2003-09-16
6622217 Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system Kourosh Gharachorloo, Mosur K. Ravishankar, Robert Stets, Andreas Nowatzyk 2003-09-16