| 6961825 |
Cache coherency mechanism using arbitration masks |
Simon C. Steely, Jr., Stephen R. Van Doren |
2005-11-01 |
$12,111,000 |
| 6904465 |
Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch |
Simon C. Steely, Jr., Stephen R. Van Doren |
2005-06-07 |
$9,928,000 |
| 6801986 |
Livelock prevention by delaying surrender of ownership upon intervening ownership request during load locked / store conditional atomic memory operation |
Simon C. Steely, Jr., Stephen R. Van Doren |
2004-10-05 |
$9,303,000 |
| 6286090 |
Mechanism for selectively imposing interference order between page-table fetches and corresponding data fetches |
Simon C. Steely, Jr., Stephen R. Van Doren, Kourosh Gharachorloo |
2001-09-04 |
$45,413,000 |
| 6279084 |
Shadow commands to optimize sequencing of requests in a switch-based multi-processor system |
Stephen R. VanDoren, Simon C. Steely, Jr., Hari K. Nagpal |
2001-08-21 |
$36,260,000 |
| 6249520 |
High-performance non-blocking switch with multiple channel ordering constraints |
Simon C. Steely, Jr., Stephen R. VanDoren, Craig D. Keefer, David Wayne Davis |
2001-06-19 |
$27,502,000 |
| 6209065 |
Mechanism for optimizing generation of commit-signals in a distributed shared-memory system |
Stephen R. Van Doren, Simon C. Steely, Jr., Kourosh Gharachorloo |
2001-03-27 |
$46,767,000 |
| 6202126 |
Victimization of clean data blocks |
Stephen R. Van Doren, Simon C. Steely, Jr. |
2001-03-13 |
$50,290,000 |
| 6154816 |
Low occupancy protocol for managing concurrent transactions with dependencies |
Simon C. Steely, Jr., Stephen R. VanDoren |
2000-11-28 |
$99,736,000 |
| 6122714 |
Order supporting mechanisms for use in a switch-based multi-processor system |
Stephen R. VanDoren, Simon C. Steely, Jr., David Fenwick |
2000-09-19 |
$51,516,000 |
| 6108737 |
Method and apparatus for reducing latency of inter-reference ordering in a multiprocessor system |
Stephen R. Van Doren, Kourosh Gharachorloo, Simon C. Steely, Jr. |
2000-08-22 |
$97,982,000 |
| 6101420 |
Method and apparatus for disambiguating change-to-dirty commands in a switch based multi-processing system with coarse directories |
Stephen R. VanDoren, Simon C. Steely, Jr., Kourosh Gharachorloo |
2000-08-08 |
$60,022,000 |
| 6094686 |
Multi-processor system for transferring data without incurring deadlock using hierarchical virtual channels |
— |
2000-07-25 |
$150,864,000 |
| 6088771 |
Mechanism for reducing latency of memory barrier operations on a multiprocessor system |
Simon C. Steely, Jr., Kourosh Gharachorloo, Stephen R. Van Doren |
2000-07-11 |
|
| 6085276 |
Multi-processor computer system having a data switch with simultaneous insertion buffers for eliminating arbitration interdependencies |
Stephen R. VanDoren |
2000-07-04 |
|
| 6085263 |
Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor |
Chester Pawlowski, Kourosh Gharachorloo, Stephen R. Van Doren, Simon C. Steely, Jr. |
2000-07-04 |
|
| 6055605 |
Technique for reducing latency of inter-reference ordering using commit signals in a multiprocessor system having shared caches |
Simon C. Steely, Jr., Kourosh Gharachorloo, Stephen R. Van Doren |
2000-04-25 |
$64,870,000 |
| 6014690 |
Employing multiple channels for deadlock avoidance in a cache coherency protocol |
Stephen R. VanDoren, Simon C. Steely, Jr. |
2000-01-11 |
|
