Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11586514 | High reliability fault tolerant computer architecture | Chester Pawlowski, John M. Chaves, Andrew Alden, Christopher D. Cotton, Michael J. Egan | 2023-02-21 |
| 6353877 | Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write | Samuel H. Duncan, Glenn Arthur Herdeg, Ricky C. Hetherington, Maurice B. Steinman, Paul Michael Guglielmi | 2002-03-05 |
| 6249520 | High-performance non-blocking switch with multiple channel ordering constraints | Simon C. Steely, Jr., Stephen R. VanDoren, Madhumitra Sharma, David Wayne Davis | 2001-06-19 |
| 6128711 | Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes | Samuel H. Duncan, Glenn Arthur Herdeg, Ricky C. Hetherington, Maurice B. Steinman, Paul Michael Guglielmi | 2000-10-03 |
| 6012120 | Method and apparatus for providing DMA transfers between devices coupled to different host bus bridges | Samuel H. Duncan, Thomas Adam McLaughlin, Paul Michael Guglielmi | 2000-01-04 |
| 5953538 | Method and apparatus providing DMA transfers between devices coupled to different host bus bridges | Samuel H. Duncan, Thomas Adam McLaughlin, Paul Michael Guglielmi | 1999-09-14 |