Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6353877 | Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line write | Samuel H. Duncan, Glenn Arthur Herdeg, Ricky C. Hetherington, Craig D. Keefer, Maurice B. Steinman | 2002-03-05 |
| 6128711 | Performance optimization and system bus duty cycle reduction by I/O bridge partial cache line writes | Samuel H. Duncan, Glenn Arthur Herdeg, Ricky C. Hetherington, Craig D. Keefer, Maurice B. Steinman | 2000-10-03 |
| 6012120 | Method and apparatus for providing DMA transfers between devices coupled to different host bus bridges | Samuel H. Duncan, Craig D. Keefer, Thomas Adam McLaughlin | 2000-01-04 |
| 5953538 | Method and apparatus providing DMA transfers between devices coupled to different host bus bridges | Samuel H. Duncan, Craig D. Keefer, Thomas Adam McLaughlin | 1999-09-14 |
| 5172011 | Latch circuit and method with complementary clocking and level sensitive scan capability | Dale H. Leuthold | 1992-12-15 |
| 4712190 | Self-timed random access memory chip | Ronald J. Melanson, Alan Kotok | 1987-12-08 |