Issued Patents All Time
Showing 26–39 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6216190 | System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Robert A. Lester +1 more | 2001-04-10 |
| 6209052 | System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Robert A. Lester +1 more | 2001-03-27 |
| 6202101 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Robert A. Lester +1 more | 2001-03-13 |
| 6199118 | System and method for aligning an initial cache line of data read from an input/output device by a central processing unit | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Robert A. Lester +1 more | 2001-03-06 |
| 6160562 | System and method for aligning an initial cache line of data read from local memory by an input/output device | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Robert A. Lester +1 more | 2000-12-12 |
| 6078338 | Accelerated graphics port programmable memory access arbiter | Ronald T. Horan, Gregory N. Santos, Robert A. Lester, Gary J. Piccirillo | 2000-06-20 |
| 5999743 | System and method for dynamically allocating accelerated graphics port memory space | Ronald T. Horan, Gregory N. Santos, Robert A. Lester, Robert C. Elliot | 1999-12-07 |
| 5999198 | Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device | Ronald T. Horan, Gregory N. Santos, Robert A. Lester, Robert C. Elliott | 1999-12-07 |
| 5990914 | Generating an error signal when accessing an invalid memory page | Ronald T. Horan, Gregory N. Santos, Robert A. Lester, Robert C. Elliott | 1999-11-23 |
| 5986677 | Accelerated graphics port read transaction merging | Ronald T. Horan, Gregory N. Santos | 1999-11-16 |
| 5949436 | Accelerated graphics port multiple entry gart cache allocation system and method | Ronald T. Horan, Gregory N. Santos, Robert A. Lester, Jerome J. Johnson, Michael J. Collins | 1999-09-07 |
| 5936640 | Accelerated graphics port memory mapped status and control registers | Ronald T. Horan, Gregory N. Santos, Robert A. Lester, Robert C. Elliott | 1999-08-10 |
| 5914727 | Valid flag for disabling allocation of accelerated graphics port memory space | Ronald T. Horan, Gregory N. Santos, Robert A. Lester, Robert C. Elliott | 1999-06-22 |
| 5905509 | Accelerated Graphics Port two level Gart cache having distributed first level caches | Robert A. Lester, Kenneth T. Chin | 1999-05-18 |