Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8241927 | Methods relating to capacitive monitoring of layer characteristics during back end-of the-line processing | Jihong Choi, Yongsik Moon, Roderick A. Augur | 2012-08-14 |
| 7214609 | Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities | Ping Jiang, Rob Kraft, Guoqiang Xing, Karen Kirmse | 2007-05-08 |
| 7186642 | Low temperature nitride used as Cu barrier layer | Zhiping Yin, Fred Fishburn | 2007-03-06 |
| 6984893 | Low temperature nitride used as Cu barrier layer | Zhiping Yin, Fred Fishburn | 2006-01-10 |
| 6734477 | Fabricating an embedded ferroelectric memory cell | Ted S. Moise, Scott R. Summerfelt, Scott Johnson | 2004-05-11 |
| 6492267 | Low temperature nitride used as Cu barrier layer | Zhiping Yin, Fred Fishburn | 2002-12-10 |
| 6358849 | Integrated circuit interconnect and method | Robert H. Havemann, Girish Dixit, Manoj Kumar Jain, Qi-Zhong Hong, Jeffrey Alan West | 2002-03-19 |
| 6251771 | Hydrogen passivation of chemical-mechanically polished copper-containing layers | Patricia B. Smith, Girish Dixit, Stephen W. Russell | 2001-06-26 |
| 6246120 | Sidewalls for guiding the via etch | Kenneth D. Brennan, David B. Aldrich, Peter S. McAnally | 2001-06-12 |
| 6074943 | Sidewalls for guiding the via etch | Kenneth D. Brennan, David B. Aldrich, Peter S. McAnally | 2000-06-13 |