| 11289495 |
Static random access memory (SRAM) bit cell circuits with a minimum distance between a storage circuit active region and a read port circuit active region to reduce area and SRAM bit cell array circuits |
Rahul Biradar, Sunil Sharma, Channappa Desai |
2022-03-29 |
| 11251123 |
Static random access memory (SRAM) bit cells employing asymmetric width read and write word lines, and related methods |
Sunil Sharma, Rahul Biradar |
2022-02-15 |
| 11092646 |
Determining a voltage and/or frequency for a performance mode |
Changho Jung, Chulmin Jung |
2021-08-17 |
| 10916275 |
Write driver and pre-charge circuitry for high performance pseudo-dual port (PDP) memories |
Changho Jung |
2021-02-09 |
| 9905316 |
Efficient sense amplifier shifting for memory redundancy |
Changho Jung |
2018-02-27 |
| 9858988 |
Timing circuit for memories |
Changho Jung |
2018-01-02 |
| 9685210 |
Overlapping precharge and data write |
Changho Jung |
2017-06-20 |
| 9564375 |
Structures and methods for extraction of device channel width |
Randy W. Mann, Sandeep Puri, Anuj Gupta, Xusheng Wu |
2017-02-07 |
| 9484300 |
Device resulting from printing minimum width semiconductor features at non-minimum pitch |
Randy W. Mann, Norman Chen, Shaowen Gao |
2016-11-01 |
| 9263349 |
Printing minimum width semiconductor features at non-minimum pitch and resulting device |
Randy W. Mann, Norman Chen, Shaowen Gao |
2016-02-16 |
| 8238187 |
Fast cyclic decoder circuit for FIFO/LIFO data buffer |
Animesh Jain, Nagendra Chandrakar |
2012-08-07 |
