Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10423277 | Interference reduction circuit for touch system | Srinath Hosur, Ashish Khandelwal | 2019-09-24 |
| 9602318 | Closed-loop high-speed channel equalizer adaptation | Roland Sperlich, Huanzhang Huang | 2017-03-21 |
| 9154133 | ESD robust level shifter | Muhammad Yusuf Ali, Rajkumar Sankaralingam | 2015-10-06 |
| 9130792 | Closed-loop high-speed channel equalizer adaptation | Roland Sperlich, Huanzhang Huang | 2015-09-08 |
| 8692592 | Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality | Steven Craig Bartling, Dharin N. Shah | 2014-04-08 |
| 7908535 | Scan testable register file | Steven Craig Bartling | 2011-03-15 |
| 7650549 | Digital design component with scan clock generation | Steven Craig Bartling, Marc Royer, Cory Dean Stewart | 2010-01-19 |
| 7644383 | Method and system for correcting signal integrity crosstalk violations | Steven Craig Bartling, Marc Royer | 2010-01-05 |
| 7626850 | Systems and devices for implementing sub-threshold memory devices | Steven Craig Bartling | 2009-12-01 |
| 7596732 | Digital storage element architecture comprising dual scan clocks and gated scan output | Steven Craig Bartling, Dharin N. Shah | 2009-09-29 |
| 7587577 | Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content | Marc Royer, Bharath Siravara, Steven Craig Bartling, Pedro R. Galabert, Neeraj Mogotra +1 more | 2009-09-08 |
| 7487417 | Digital storage element with enable signal gating | Steven Craig Bartling, Dharin N. Shah | 2009-02-03 |
| 7425859 | Apparatus and method for generating pulses | Steven Craig Bartling | 2008-09-16 |
| 7375567 | Digital storage element architecture comprising dual scan clocks and preset functionality | Steven Craig Bartling | 2008-05-20 |
| 7345518 | Digital storage element with dual behavior | Steven Craig Bartling, Dharin N. Shah, James R. Hochschild | 2008-03-18 |
| 7315191 | Digital storage element architecture comprising dual scan clocks and reset functionality | Steven Craig Bartling | 2008-01-01 |
| 7274233 | Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality | Steven Craig Bartling, Dharin N. Shah | 2007-09-25 |
| 7274234 | Digital storage element architecture comprising integrated multiplexer and reset functionality | Steven Craig Bartling, Dharin N. Shah | 2007-09-25 |
| 7236036 | Apparatus and method for generating pulses | Steven Craig Bartling | 2007-06-26 |
| 7031836 | Grid mapping utility for a GPS device | — | 2006-04-18 |
| 6690242 | Delay circuit with current steering output symmetry and supply voltage insensitivity | Lieyi Fang, Kuok Ling, Feng Ying | 2004-02-10 |
| 6650191 | Low jitter ring oscillator architecture | Lieyi Fang, Daramana Gata, James R. Hochschild | 2003-11-18 |