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Optimizing use of computer resources in implementing circuit designs through machine learning |
Karthic P, Paul D. Kundarewich, Satish B. Sivaswamy, Meghraj Kalase, Vishal Tripathi +3 more |
2024-06-25 |
| 11714950 |
Automated timing closure on circuit designs |
Veeresh Pratap Singh, Meghraj Kalase, John Blaine, Padmini Gopalakrishnan, Frederic Revenu +4 more |
2023-08-01 |
| 11586791 |
Visualization of data buses in circuit designs |
Anup Hosangadi, Aman Gayasen, Padmini Gopalakrishnan |
2023-02-21 |
| 11003826 |
Automated analysis and optimization of circuit designs |
Padmini Gopalakrishnan, Vishal Tripathy, Vikas N. Vedamurthy, Sumit Nagpal |
2021-05-11 |
| 10867093 |
System and method for an electronic design tool providing automated guidance and interface for circuit design processing |
John Blaine, Meghraj Kalase, Frederic Revenu, Veeresh Pratap Singh, Satish Bachina +4 more |
2020-12-15 |
| 9501604 |
Testing critical paths of a circuit design |
Geetesh MORE, Nagaraj Savithri |
2016-11-22 |
| 8473881 |
Multi-resource aware partitioning for integrated circuits |
Wei Mark Fang, Vishal Suthar |
2013-06-25 |
| 8448122 |
Implementing sub-circuits with predictable behavior within a circuit design |
Vishal Suthar, Hasan Arslan, Sridhar Krishnamurthy, Sanjeev Kwatra, Rajat Aggarwal +1 more |
2013-05-21 |
| 8418115 |
Routability based placement for multi-die integrated circuits |
Marvin Tom, Rajat Aggarwal |
2013-04-09 |
| 8312405 |
Method of placing input/output blocks on an integrated circuit device |
Victor Z. Slonim, Rajat Aggarwal, Guenter Stenz |
2012-11-13 |
| 8230377 |
Control set constraint driven force directed analytical placer for programmable integrated circuits |
Wei Mark Fang |
2012-07-24 |
| 8225262 |
Method of and system for placing clock circuits in an integrated circuit |
Marvin Tom, Wei Mark Fang |
2012-07-17 |
| 8091060 |
Clock domain partitioning of programmable integrated circuits |
Marvin Tom |
2012-01-03 |
| 7735039 |
Methods of estimating net delays in tile-based PLD architectures |
Hasan Arslan, Meng Lou, Anirban Rahut |
2010-06-08 |
| 7636876 |
Cost-based performance driven legalization technique for placement in logic designs |
Sankaranarayanan Srinivasan |
2009-12-22 |
| 7392499 |
Placement of input/output blocks of an electronic design in an integrated circuit |
Guenter Stenz |
2008-06-24 |
| 7313778 |
Method system and apparatus for floorplanning programmable logic designs |
Guenter Stenz, Rajat Aggarwal, James L. Saunders |
2007-12-25 |
| 7240315 |
Automated local clock placement for FPGA designs |
Qiang Wang, Sudip K. Nag, James L. Saunders, Pavanish Nirula |
2007-07-03 |
| 7149993 |
Method, system, and apparatus for incremental design in programmable logic devices using floorplanning |
Rajat Aggarwal, Guenter Stenz |
2006-12-12 |
| 7149994 |
Integrated clock and input output placer |
Qiang Wang |
2006-12-12 |
| 7143380 |
Method for application of network flow techniques under constraints |
Jason H. Anderson, Sudip K. Nag, Guenter Stenz |
2006-11-28 |
| 6857115 |
Placement of objects with partial shape restriction |
Guenter Stenz, Sudip K. Nag, Jason H. Anderson |
2005-02-15 |
| 6789244 |
Placement of clock objects under constraints |
Guenter Stenz, Sudip K. Nag |
2004-09-07 |