Pavanish Nirula — 1 Patent at AMD

Pavanish Nirula has been granted 1 US patent while listed as an inventor at AMD. All of these patents were granted in 2007. Pavanish Nirula ranks #2,406,284 of 4,157,543 US inventors in our database (top 57.9%). Patent records list Pavanish Nirula in San Jose, CA, US.

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Showing 1–1 of 1 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
7240315	Automated local clock placement for FPGA designs	Qiang Wang, Sudip K. Nag, Srinivasan Dasasathyan, James L. Saunders	2007-07-03	$12,485,000

Pavanish Nirula — 1 Patent

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