Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12301229 | Adaptive voltage scaling using temperature and performance sensors | Jose Luis Flores, Anthony M. Hill | 2025-05-13 |
| 12212317 | Stress reduction on stacked transistor circuits | Erkan Bilhan | 2025-01-28 |
| 11881275 | Screening of memory circuits | Devanathan Varadarajan, Anthony M. Hill | 2024-01-23 |
| 11831309 | Stress reduction on stacked transistor circuits | Erkan Bilhan | 2023-11-28 |
| 11626875 | Stress reduction on stacked transistor circuits | Erkan Bilhan | 2023-04-11 |
| 11568951 | Screening of memory circuits | Devanathan Varadarajan, Anthony M. Hill | 2023-01-31 |
| 8890588 | Circuits and methods for asymmetric aging prevention | Kalpesh Amrutlal Shah, Arvind Kumar | 2014-11-18 |
| 8144533 | Compensatory memory system | — | 2012-03-27 |
| 7446552 | Semiconductor device testing | Juan Carlos Martinez | 2008-11-04 |
| 7446553 | Semiconductor device testing | Juan Carlos Martinez | 2008-11-04 |
| 7382147 | Semiconductor device testing | Juan Carlos Martinez | 2008-06-03 |
| 7365556 | Semiconductor device testing | Juan Carlos Martinez | 2008-04-29 |
| 6581201 | Method for power routing and distribution in an integrated circuit with multiple interconnect layers | David Thomas, Clive Bittlestone | 2003-06-17 |
| 6381704 | Method and apparatus for altering timing relationships of non-overlapping clock signals in a microprocessor | Rajib Nag, Robert E. Farrell | 2002-04-30 |
| 6363516 | Method for hierarchical parasitic extraction of a CMOS design | Nagaraj Savithri, Vijaya Gunturi | 2002-03-26 |
| 6308307 | Method for power routing and distribution in an integrated circuit with multiple interconnect layers | David Thomas, Clive Bittlestone | 2001-10-23 |
| 6253359 | Method for analyzing circuit delays caused by capacitive coupling in digital circuits | Nagaraj Savithri, Deepak Kapoor | 2001-06-26 |
| 6038383 | Method and apparatus for determining signal line interconnect widths to ensure electromigration reliability | Duane J. Young, Nagaraj Savithri, Haldun Haznedar | 2000-03-14 |
| 5835421 | Method and apparatus for reducing failures due to bit line coupling and reducing power consumption in a memory | Luat Q. Pham | 1998-11-10 |
| 5745421 | Method and apparatus for self-timed precharge of bit lines in a memory | Luat Q. Pham | 1998-04-28 |