Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12261612 | Compact frequency-locked loop architecture for digital clocking | John Abcarius, Debesh Bhatta, Andrew Weil, Wenjing Yin | 2025-03-25 |
| 9639640 | Generation of delay values for a simulation model of circuit elements in a clock network | Nagaraj Savithri, Chiao Kai Hwang | 2017-05-02 |
| 9148192 | Transceiver for providing a clock signal | Alan Wong, Christopher J. Borrelli, Loren Jones, Seu Wah Low, Parag Upadhyaya +1 more | 2015-09-29 |
| 8937491 | Clock network architecture | Brian C. Gaide, Steven P. Young, Trevor J. Bauer, Dinesh D. Gaitonde | 2015-01-20 |
| 7564264 | Preventing transistor damage | Shawn K. Morrison, James J. Koning, Greg Starr, John D. Logue | 2009-07-21 |
| 7535278 | Circuits and methods of using parallel counter controlled delay lines to generate a clock signal | Raymond C. Pang, Kwansuhk Oh | 2009-05-19 |
| 7477112 | Structure for the main oscillator of a counter-controlled delay line | Tao Pi, Alireza S. Kaviani | 2009-01-13 |