Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12261612 | Compact frequency-locked loop architecture for digital clocking | Debesh Bhatta, Andrew Weil, Robert M. Ondris, Wenjing Yin | 2025-03-25 |
| 11614763 | Reference voltage generator based on threshold voltage difference of field effect transistors | Debesh Bhatta, Sulin Li, Shitong Zhao, Hui Wang | 2023-03-28 |
| 10958279 | Partitioned digital-to-analog converter system | Debesh Bhatta, Kevin Jia-Nong Wang, Karthik Nagarajan, Andrew Weil, Christian Venerus +1 more | 2021-03-23 |
| 10447282 | Phase locked loop (PLL) | — | 2019-10-15 |