Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 12483257 | Dynamic current mismatch accumulation schemes for digital-to-analog converters | Sarthak Kalani, Andreas Weil | 2025-11-25 | |
| 12261612 | Compact frequency-locked loop architecture for digital clocking | Debesh Bhatta, Andrew Weil, Robert M. Ondris, Wenjing Yin | 2025-03-25 | |
| 11614763 | Reference voltage generator based on threshold voltage difference of field effect transistors | Debesh Bhatta, Sulin Li, Shitong Zhao, Hui Wang | 2023-03-28 | $12,086,000 |
| 10958279 | Partitioned digital-to-analog converter system | Debesh Bhatta, Kevin Jia-Nong Wang, Karthik Nagarajan, Andrew Weil, Christian Venerus +1 more | 2021-03-23 | $20,497,000 |
| 10447282 | Phase locked loop (PLL) | — | 2019-10-15 | $10,854,000 |