Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11038768 | Method and system for correlation of a behavioral model to a circuit realization for a communications system | Ivan O. Madrigal, Michael O. Jenkins, Hong S. Ahn, Murtuza Z. Cutleriwala, Alan Wong +3 more | 2021-06-15 |
| 10812089 | Apparatus and method to reduce lock time via frequency band calibration | Caleb S. Leung, Edward Lee, Alan Wong, Yohan Frans | 2020-10-20 |
| 10749729 | System and method for automatic gain control adaptation | Alan Wong, Hong S. Ahn, Edward Lee | 2020-08-18 |
| 9960902 | Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit | Winson Lin, Yu Xu, Caleb S. Leung, Alan Wong, Yohan Frans +1 more | 2018-05-01 |
| 9882703 | Resolving meta-stability in a clock and data recovery circuit | Yu Xu, Winson Lin, Caleb S. Leung, Alan Wong, Yohan Frans +1 more | 2018-01-30 |
| 9800438 | Built-in eye scan for ADC-based receiver | Hongtao Zhang, Zhaoyin D. Wu, Geoffrey Zhang | 2017-10-24 |
| 9209960 | Fast locking CDR for burst mode | Caleb S. Leung, Alan Wong, Yu Xu, Yohan Frans, Kun-Yung Chang | 2015-12-08 |
| 9148192 | Transceiver for providing a clock signal | Alan Wong, Loren Jones, Seu Wah Low, Parag Upadhyaya, Robert M. Ondris +1 more | 2015-09-29 |
| 9065601 | Circuits for and methods of implementing a receiver in an integrated circuit device | Michael O. Jenkins, Cheng-Hsiang Hsieh | 2015-06-23 |
| 8386828 | Circuit for estimating latency through a FIFO buffer | Sai Lalith Chaitanya Ambatipudi, Seu Wah Low, Loren Jones | 2013-02-26 |
| 7424553 | Method and apparatus for communicating data between a network transceiver and memory circuitry | Paul M. Hartke, Glenn A. Baxter | 2008-09-09 |
| 7225278 | Method and apparatus for controlling direct access to memory circuitry | Glenn A. Baxter | 2007-05-29 |