| 10742453 |
Nonlinear equalizer with nonlinearity compensation |
Min-Yuan Wu, Hongtao Zhang |
2020-08-11 |
$21,078,000 |
| 10644844 |
Circuit for and method of determining error spacing in an input signal |
Winson Lin, Hongtao Zhang, Geoffrey Zhang |
2020-05-05 |
$31,719,000 |
| 10404408 |
Pam multi-level error distribution signature capture |
Winson Lin, Hongtao Zhang, Geoffrey Zhang |
2019-09-03 |
$30,588,000 |
| 10256968 |
Systems and methods for clock and data recovery |
Zhaoyin D. Wu, Winson Lin, Yohan Frans, Geoffrey Zhang |
2019-04-09 |
$88,620,000 |
| 10038545 |
Systems and methods for clock and data recovery |
Zhaoyin D. Wu, Winson Lin, Geoffrey Zhang |
2018-07-31 |
$15,644,000 |
| 9960902 |
Temporal change in data-crossing clock phase difference to resolve meta-stability in a clock and data recovery circuit |
Winson Lin, Caleb S. Leung, Alan Wong, Christopher J. Borrelli, Yohan Frans +1 more |
2018-05-01 |
$29,690,000 |
| 9882703 |
Resolving meta-stability in a clock and data recovery circuit |
Winson Lin, Caleb S. Leung, Alan Wong, Christopher J. Borrelli, Yohan Frans +1 more |
2018-01-30 |
$13,591,000 |
| 9882795 |
Signal loss detector |
Hongtao Zhang, Geoffrey Zhang, Patrick Satarzadeh, Zhaoyin D. Wu |
2018-01-30 |
$13,591,000 |
| 9413524 |
Dynamic gain clock data recovery in a receiver |
Yohan Frans, Kun-Yung Chang |
2016-08-09 |
$8,970,000 |
| 9379720 |
Clock recovery circuit |
Santiago G. Asuncion, Tianqi Tang, Toan Duc Pham, Kun-Yung Chang |
2016-06-28 |
$4,436,000 |
| 9379880 |
Clock recovery circuit |
Yohan Frans, Kun-Yung Chang |
2016-06-28 |
$4,436,000 |
| 9356775 |
Clock data recovery (CDR) phase walk scheme in a phase-interpolater-based transceiver system |
Cheng-Hsiang Hsieh, Yohan Frans, Kun-Yung Chang |
2016-05-31 |
$11,154,000 |
| 9209960 |
Fast locking CDR for burst mode |
Caleb S. Leung, Alan Wong, Christopher J. Borrelli, Yohan Frans, Kun-Yung Chang |
2015-12-08 |
$14,224,000 |
| 8253451 |
Clock data recovery using phase accumulation over a time period defined by a number of cycles of a clock signal |
Cheng-Hsiang Hsieh, Mengchi Liu |
2012-08-28 |
$40,129,000 |
| 7555667 |
Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry |
Ali Burney, Leon Zheng, Sanjay K. Charagulla |
2009-06-30 |
$14,977,000 |
| 7460040 |
High-speed serial interface architecture for a programmable logic device |
Thungoc M. Tran, Kwong-Wen Wei, Sergey Shumarayev |
2008-12-02 |
$8,569,000 |
