Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12327077 | Deadlock detection and prevention for routing packet-switched nets in electronic systems | Sreesan Venkatakrishnan, Satish B. Sivaswamy | 2025-06-10 |
| 11875100 | Distributed parallel processing routing | Satish B. Sivaswamy, Ashot Shakhkyan, Garik Mkrtchyan, Guenter Stenz, Bhasker Pinninti | 2024-01-16 |
| 11733980 | Application implementation and buffer allocation for a data processing engine array | Brian Guttag, Satish B. Sivaswamy | 2023-08-22 |
| 11604751 | Optimizing hardware design throughput by latency aware balancing of re-convergent paths | Brian Guttag, Sreesan Venkatakrishnan, Satish B. Sivaswamy | 2023-03-14 |
| 11238206 | Partition wire assignment for routing multi-partition circuit designs | Satish B. Sivaswamy, Garik Mkrtchyan, Grigor S. Gasparyan | 2022-02-01 |
| 9460302 | Method and system for shielding data in transit and data in memory | Sumedh W. Sathaye | 2016-10-04 |
| 9336363 | Method and system for secure deployment of information technology (IT) solutions in untrusted environments | Sumedh W. Sathaye | 2016-05-10 |
| 9209971 | Method and system for shielding data in untrusted environments | Sumedh W. Sathaye | 2015-12-08 |
| 7755388 | Interconnect structure enabling indirect routing in programmable logic | Kailash Digari | 2010-07-13 |
| 7414433 | Interconnect structure enabling indirect routing in programmable logic | Kailash Digari | 2008-08-19 |
| 7307452 | Interconnect structure enabling indirect routing in programmable logic | Kailash Digari | 2007-12-11 |
| 6864714 | PLDs providing reduced delays in cascade chain circuits | Kailash Digari | 2005-03-08 |