Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11875100 | Distributed parallel processing routing | Satish B. Sivaswamy, Ashot Shakhkyan, Nitin Deshmukh, Guenter Stenz, Bhasker Pinninti | 2024-01-16 |
| 11790139 | Predicting a performance metric based on features of a circuit design and explaining marginal contributions of the features to the prediction | Satish B. Sivaswamy | 2023-10-17 |
| 11709521 | Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG) | Frederic Revenu, Frank Mueller, Thomas O. Satter, Mehrdad Eslami Dehkordi, Satish B. Sivaswamy +2 more | 2023-07-25 |
| 11238206 | Partition wire assignment for routing multi-partition circuit designs | Satish B. Sivaswamy, Nitin Deshmukh, Grigor S. Gasparyan | 2022-02-01 |
| 11108644 | Data processing engine (DPE) array routing | Satish B. Sivaswamy, Jinny Singh | 2021-08-31 |
| 8959474 | Routing multi-fanout nets | Grigor S. Gasparyan | 2015-02-17 |