Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG)

Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG)

US Patent 11709521 · Granted Jul 25, 2023

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Clock synchronization method and apparatus, and electronic device2025
Drive train2025
Deadlock detection and prevention for routing packet-switched nets in electronic2025
Building block2025
Optimizing use of computer resources in implementing circuit designs through mac2024
Distributed parallel processing routing2024
Distributed parallel processing routing2024
Input/output station for a field bus system, field bus coupler for the input/out2024
Predicting a performance metric based on features of a circuit design and explai2023
Predicting a performance metric based on features of a circuit design and explai2023
Application implementation and buffer allocation for a data processing engine ar2023
Automated timing closure on circuit designs2023