Issued Patents All Time
Showing 1–25 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10393796 | Testing integrated circuits during split fabrication | Bishnu P. Das, Kaushik Vaidyanathan | 2019-08-27 |
| 10026431 | Magnetic shift register | David M. Bromberg, Jian Zhu | 2018-07-17 |
| 9524767 | Bitcell wth magnetic switching elements | David M. Bromberg, Huseyin Ekin Sumbul | 2016-12-20 |
| 9300301 | Nonvolatile magnetic logic device | David M. Bromberg, Jian Zhu, Vincent Sokalski, Matthew Moneck | 2016-03-29 |
| 9286216 | 3DIC memory chips including computational logic-in-memory for performing accelerated data processing | Franz Franchetti, Qiuling Zhu | 2016-03-15 |
| 9117523 | Chainlink memory | Daniel Henry Morris, David M. Bromberg, Jiam-Gang (Jimmy) Zhu | 2015-08-25 |
| 8589833 | Method for the definition of a library of application-domain-specific logic cells | Dipti Motiani, Veerbhan Kheterpal | 2013-11-19 |
| 8476925 | Magnetic switching cells and methods of making and operating same | Jian Zhu | 2013-07-02 |
| 8400066 | Magnetic logic circuits and systems incorporating same | Jian Zhu | 2013-03-19 |
| 8271916 | Method for the definition of a library of application-domain-specific logic cells | Dipti Motiani, Veerbhan Kheterpal | 2012-09-18 |
| 8198655 | Regular pattern arrays for memory and logic on a semiconductor substrate | Daniel Henry Morris | 2012-06-12 |
| 7945868 | Tunable integrated circuit design for nano-scale technologies | Xin Li | 2011-05-17 |
| 7908131 | Method for parameterized model order reduction of integrated circuit interconnects | Xin Li, Peng Li | 2011-03-15 |
| 7906254 | Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features | Andrzej Strojwas, Lucio Lanza | 2011-03-15 |
| 7827516 | Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns | Matthew Moe, Vyacheslav Rovner, Thiago Hersan, Dipti Motiani, Veerbhan Kheterpal | 2010-11-02 |
| 7784013 | Method for the definition of a library of application-domain-specific logic cells | Dipti Motiani, Veerbhan Kheterpal | 2010-08-24 |
| 7757187 | Method for mapping a Boolean logic network to a limited set of application-domain specific logic cells | Veerbhan Kheterpal, Dipti Motiani | 2010-07-13 |
| 7634248 | Configurable circuits using phase change switches | Yang Xu, Mehdi Asheghi | 2009-12-15 |
| 7487486 | Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations | Mustafa Celik, Jiayong Le, Xin Li | 2009-02-03 |
| 7350164 | Optimization and design method for configurable analog circuits and devices | Yang Xu, Stephen P. Boyd | 2008-03-25 |
| 7325180 | System and method to test integrated circuits on a wafer | Chik Patrick Yue, R. Blanton, Thomas Vogels | 2008-01-29 |
| 7278118 | Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features | Andrzej Strojwas, Lucio Lanza | 2007-10-02 |
| 7096174 | Systems, methods and computer program products for creating hierarchical equivalent circuit models | Michael Beattie | 2006-08-22 |
| 6961916 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Sharad Malik, Feroze P. Taraporevala, Abhijeet Chakraborty, Gary K. Yeap +4 more | 2005-11-01 |
| 6820245 | Methods, systems, and computer program products for modeling inductive effects in a circuit by combining a plurality of localized models | Michael Beattie | 2004-11-16 |