Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7827516 | Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns | Matthew Moe, Lawrence Pileggi, Vyacheslav Rovner, Dipti Motiani, Veerbhan Kheterpal | 2010-11-02 |