Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11107804 | IC with test structures and e-beam pads embedded within a contiguous standard cell area | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +21 more | 2021-08-31 |
| 11081476 | IC with test structures and e-beam pads embedded within a contiguous standard cell area | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +21 more | 2021-08-03 |
| 11081477 | IC with test structures and e-beam pads embedded within a contiguous standard cell area | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +21 more | 2021-08-03 |
| 11075194 | IC with test structures and E-beam pads embedded within a contiguous standard cell area | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +21 more | 2021-07-27 |
| 11018126 | IC with test structures and e-beam pads embedded within a contiguous standard cell area | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +21 more | 2021-05-25 |
| 10978438 | IC with test structures and E-beam pads embedded within a contiguous standard cell area | Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli +21 more | 2021-04-13 |
| 7827516 | Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns | Lawrence Pileggi, Vyacheslav Rovner, Thiago Hersan, Dipti Motiani, Veerbhan Kheterpal | 2010-11-02 |