Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12112108 | Method to compute timing yield and yield bottleneck using correlated sample generation and efficient statistical simulation | Wenwen Chai, Li Ding | 2024-10-08 |
| 11288426 | Analyzing delay variations and transition time variations for electronic circuits | Duc Huynh, Ayhan Mutlu, Peivand Tehrani | 2022-03-29 |
| 10783301 | Analyzing delay variations and transition time variations for electronic circuits | Duc Huynh, Ayhan Mutlu, Peivand Tehrani | 2020-09-22 |
| 10755023 | Circuit timing analysis | Gregory T. Schulte, Brandon Thompson, Richard Moloney, Adrian Wrixon | 2020-08-25 |
| 10255395 | Analyzing delay variations and transition time variations for electronic circuits | Duc Huynh, Ayhan Mutlu, Peivand Tehrani | 2019-04-09 |
| 9424380 | Augmented simulation method for waveform propagation in delay calculation | Peivand Tehrani, Li Ding, Xin Wang, Ahmed Shebaita | 2016-08-23 |
| 8843864 | Statistical corner evaluation for complex on-chip variation model | Mustafa Celik, Guy Maor, Ayhan Mutlu | 2014-09-23 |
| 8713501 | Dual-box location aware and dual-bitmap voltage domain aware on-chip variation techniques | Feroze P. Taraporevala | 2014-04-29 |
| 8555222 | Statistical corner evaluation for complex on chip variation model | Mustafa Celik, Guy Maor, Ayhan Mutlu | 2013-10-08 |
| 8495544 | Statistical delay and noise calculation considering cell and interconnect variations | Mustafa Celik | 2013-07-23 |
| 8407640 | Sensitivity-based complex statistical modeling for random on-chip variation | Mustafa Celik, Guy Maor, Ayhan Mutlu | 2013-03-26 |
| 7890915 | Statistical delay and noise calculation considering cell and interconnect variations | Mustafa Celik | 2011-02-15 |
| 7487486 | Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations | Mustafa Celik, Lawrence Pileggi, Xin Li | 2009-02-03 |