Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8713501 | Dual-box location aware and dual-bitmap voltage domain aware on-chip variation techniques | Jiayong Le | 2014-04-29 |
| 8666722 | Efficient data compression for vector-based static timing analysis | Jinfeng Liu, Brian Clerkin | 2014-03-04 |
| 8615727 | Simultaneous multi-corner static timing analysis using samples-based static timing infrastructure | Praveen Ghanta, Amit Goel, Marina Ovchinnikov, Jinfeng Liu, Kayhan Kucukcakar | 2013-12-24 |
| 8321824 | Multiple-power-domain static timing analysis | Jindrich Zejda, William Chiu-Ting Shu, Khalid Rahmat | 2012-11-27 |
| 8204730 | Generating variation-aware library data with efficient device mismatch characterization | Jinfeng Liu | 2012-06-19 |
| 7774731 | Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis | Ali Dasdan, Emre Salman, Kayhan Kucukcakar | 2010-08-10 |
| 7506293 | Characterizing sequential cells using interdependent setup and hold times, and utilizing the sequential cell characterizations in static timing analysis | Ali Dasdan, Emre Salman, Kayhan Kucukcakar | 2009-03-17 |
| 6961916 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Abhijeet Chakraborty, Gary K. Yeap +4 more | 2005-11-01 |
| 6442743 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Abhijeet Chakraborty, Gary K. Yeap +4 more | 2002-08-27 |
| 6385760 | System and method for concurrent placement of gates and associated wiring | Lawrence Pileggi, Majid Sarrafzadeh, Gary K. Yeap, Tong Gao, Douglas B. Boyle | 2002-05-07 |
| 6286128 | Method for design optimization using logical and physical information | Lawrence Pileggi, Majid Sarrafzadeh, Sharad Malik, Abhijeet Chakraborty, Archie Li +17 more | 2001-09-04 |