PG

Praveen Ghanta

CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
SY Synopsys: 2 patents #669 of 2,302Top 30%
TR The Arizona Board Of Regents: 1 patents #129 of 428Top 35%
📍 Cupertino, CA: #2,110 of 6,989 inventorsTop 35%
🗺 California: #82,707 of 386,348 inventorsTop 25%
Overall (All Time): #705,640 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
11741282 Reinforcement learning-based adjustment of digital circuits Siddhartha Nath, Vishal Khandelwal, Yi-Chen Lu 2023-08-29
10430536 Method and apparatus for yield calculation using statistical timing data that accounts for path and stage delay correlation Igor Keller, Mikhail Chetin 2019-10-01
10275554 Delay propagation for multiple logic cells using correlation and coskewness of delays and slew rates in an integrated circuit design Mikhail Chetin, Igor Keller 2019-04-30
10185795 Systems and methods for statistical static timing analysis Igor Keller, Arun Kumar Mishra 2019-01-22
10073934 Systems and methods for statistical static timing analysis Igor Keller, Arun Kumar Mishra 2018-09-11
8615727 Simultaneous multi-corner static timing analysis using samples-based static timing infrastructure Amit Goel, Feroze P. Taraporevala, Marina Ovchinnikov, Jinfeng Liu, Kayhan Kucukcakar 2013-12-24
7630852 Method of evaluating integrated circuit system performance using orthogonal polynomials Sarma Vrudhula, Sarvesh Bhardwaj 2009-12-08