Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12327075 | System and method for clock distribution in a digital circuit | Ankit Wagle | 2025-06-10 |
| 12057831 | Threshold logic gates using flash transistors | Sunil Khatri | 2024-08-06 |
| 11599779 | Neural network circuitry having approximate multiplier units | Elham Azari | 2023-03-07 |
| 11356100 | FPGA with reconfigurable threshold logic gates for improved performance, power, and area | Ankit Wagle | 2022-06-07 |
| 10795809 | Non-volatile logic device for energy-efficient logic state restoration | Jinghua Yang, Aykut Dengi | 2020-10-06 |
| 10551869 | Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs | Aykut Dengi, Niranjan Kulkarni | 2020-02-04 |
| 10447249 | Hold violation free scan chain and scanning mechanism for testing of synchronous digital VLSI circuits | Niranjan Kulkarni | 2019-10-15 |
| 10250236 | Energy efficient, robust differential mode d-flip-flop | Niranjan Kulkarni, Jinghua Yang | 2019-04-02 |
| 10133323 | Processor control system | Vinay Hanumaiah, Benjamin Gaudette | 2018-11-20 |
| 9933825 | Determining parameters that affect processor energy efficiency | Vinay Hanumaiah | 2018-04-03 |
| 9934463 | Neuromorphic computational system(s) using resistive synaptic devices | Jae-sun Seo, Shimeng Yu, Yu Cao | 2018-04-03 |
| 9876503 | Method of obfuscating digital logic circuits using threshold voltage | Aykut Dengi, Niranjan Kulkarni, Joseph Davis | 2018-01-23 |
| 9490815 | Robust, low power, reconfigurable threshold logic array | Niranjan Kulkarni | 2016-11-08 |
| 9473139 | Threshold logic element with stabilizing feedback | Niranjan Kulkarni | 2016-10-18 |
| 9466362 | Resistive cross-point architecture for robust data representation with arbitrary precision | Shimeng Yu, Yu Cao, Jae-sun Seo, Jieping Ye | 2016-10-11 |
| 9356598 | Threshold logic gates with resistive networks | Jinghua Yang, Niranjan Kulkarni, Shimeng Yu | 2016-05-31 |
| 9306151 | Threshold gate and threshold logic array | Nishant S. Nukala, Niranjan Kulkarni | 2016-04-05 |
| 8832614 | Technology mapping for threshold and logic gate hybrid circuits | Niranjan Kulkarni | 2014-09-09 |
| 8601417 | Decomposition based approach for the synthesis of threshold logic circuits | Tejaswi Gowda | 2013-12-03 |
| 8181133 | Combinational equivalence checking for threshold logic circuits | Tejaswi Gowda | 2012-05-15 |
| 8164359 | Threshold logic element having low leakage power and high performance | Samuel Leshner | 2012-04-24 |
| 7630852 | Method of evaluating integrated circuit system performance using orthogonal polynomials | Praveen Ghanta, Sarvesh Bhardwaj | 2009-12-08 |