Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10551869 | Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs | Sarma Vrudhula, Aykut Dengi | 2020-02-04 |
| 10447249 | Hold violation free scan chain and scanning mechanism for testing of synchronous digital VLSI circuits | Sarma Vrudhula | 2019-10-15 |
| 10250236 | Energy efficient, robust differential mode d-flip-flop | Sarma Vrudhula, Jinghua Yang | 2019-04-02 |
| 9876503 | Method of obfuscating digital logic circuits using threshold voltage | Sarma Vrudhula, Aykut Dengi, Joseph Davis | 2018-01-23 |
| 9490815 | Robust, low power, reconfigurable threshold logic array | Sarma Vrudhula | 2016-11-08 |
| 9473139 | Threshold logic element with stabilizing feedback | Sarma Vrudhula | 2016-10-18 |
| 9356598 | Threshold logic gates with resistive networks | Sarma Vrudhula, Jinghua Yang, Shimeng Yu | 2016-05-31 |
| 9306151 | Threshold gate and threshold logic array | Sarma Vrudhula, Nishant S. Nukala | 2016-04-05 |
| 8832614 | Technology mapping for threshold and logic gate hybrid circuits | Sarma Vrudhula | 2014-09-09 |