GY

Gary K. Yeap

SY Synopsys: 8 patents #127 of 2,302Top 6%
MS Monterey Design Systems: 4 patents #6 of 38Top 20%
Motorola: 3 patents #3,303 of 12,470Top 30%
Overall (All Time): #313,557 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12118283 Automatic channel identification of high-bandwidth memory channels for auto-routing Xun Liu 2024-10-15
11816407 Automatic channel identification of high-bandwidth memory channels for auto-routing Xun Liu 2023-11-14
10922467 Methodology using Fin-FET transistors Bohai Liu, Gang Ni, Chunlei Zhu 2021-02-16
10817636 Methodology using Fin-FET transistors Bohai Liu, Gang Ni, Chunlei Zhu 2020-10-27
8726215 Standard cell placement technique for double patterning technology John Jung Lee, Renata Zaliznyak, Paul David Friedberg 2014-05-13
8392870 Two-chip co-design and co-optimization in three-dimensional integrated circuit net assignment Yifan Zhang, Yonghua Liao, Dalei Wang 2013-03-05
7937677 Design-for-test-aware hierarchical design planning Hung-Chun Chien, Ben Mathew, Padmashree Takkars, Bang Liu, Chang-Wei Tai +1 more 2011-05-03
6961916 Placement method for integrated circuit design using topo-clustering Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Feroze P. Taraporevala, Abhijeet Chakraborty +4 more 2005-11-01
6442743 Placement method for integrated circuit design using topo-clustering Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Feroze P. Taraporevala, Abhijeet Chakraborty +4 more 2002-08-27
6385760 System and method for concurrent placement of gates and associated wiring Lawrence Pileggi, Majid Sarrafzadeh, Feroze P. Taraporevala, Tong Gao, Douglas B. Boyle 2002-05-07
6286128 Method for design optimization using logical and physical information Lawrence Pileggi, Majid Sarrafzadeh, Sharad Malik, Abhijeet Chakraborty, Archie Li +17 more 2001-09-04
6192508 Method for logic optimization for improving timing and congestion during placement in integrated circuit design Sharad Malik, Lawrence Pileggi, Abhijeet Chakraborty, Douglas B. Boyle 2001-02-20
5825644 Method for encoding a state machine — 1998-10-20
5740407 Method of generating power vectors for circuit power dissipation simulation having both combinational and sequential logic circuits Alberto J. Reyes, Sean Tyler 1998-04-14
5673420 Method of generating power vectors for cell power dissipation simulation Alberto J. Reyes, James Patrick Garvey, II 1997-09-30