Issued Patents All Time
Showing 25 most recent of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9495295 | Photonics-optimized processor system | Birendra Dutt | 2016-11-15 |
| 8035139 | Dynamic random access memory having junction field effect transistor cell access device | — | 2011-10-11 |
| 6961916 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Feroze P. Taraporevala, Abhijeet Chakraborty +4 more | 2005-11-01 |
| 6557145 | Method for design optimization using logical and physical information | James S. Koford | 2003-04-29 |
| 6493658 | Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms | James S. Koford, Michael D. Rostoker, Edwin R. Jones, Ranko Scepanovic | 2002-12-10 |
| 6449756 | Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design | Sharad Malik, Lawrence Pileggi, Eric McCaughrin, Abhijeet Chakraborty | 2002-09-10 |
| 6442743 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Feroze P. Taraporevala, Abhijeet Chakraborty +4 more | 2002-08-27 |
| 6385760 | System and method for concurrent placement of gates and associated wiring | Lawrence Pileggi, Majid Sarrafzadeh, Gary K. Yeap, Feroze P. Taraporevala, Tong Gao | 2002-05-07 |
| 6367051 | System and method for concurrent buffer insertion and placement of logic gates | Lawrence Pileggi, Sharad Malik, Emre Tuncer, Abhijeet Chakraborty, Satyamurthy Pullela +1 more | 2002-04-02 |
| 6286128 | Method for design optimization using logical and physical information | Lawrence Pileggi, Majid Sarrafzadeh, Sharad Malik, Abhijeet Chakraborty, Archie Li +17 more | 2001-09-04 |
| 6192508 | Method for logic optimization for improving timing and congestion during placement in integrated circuit design | Sharad Malik, Lawrence Pileggi, Abhijeet Chakraborty, Gary K. Yeap | 2001-02-20 |
| 6155725 | Cell placement representation and transposition for integrated circuit physical design automation system | Ranko Scepanovic, James S. Koford, Edwin R. Jones, Michael D. Rostoker | 2000-12-05 |
| 6118870 | Microprocessor having instruction set extensions for decryption and multimedia applications | Michael D. Rostoker | 2000-09-12 |
| 6099580 | Method for providing performance-driven logic optimization in an integrated circuit layout design | James S. Koford | 2000-08-08 |
| 6092229 | Single chip systems using general purpose processors | Michael D. Rostoker | 2000-07-18 |
| 5963975 | Single chip integrated circuit distributed shared memory (DSM) and communications nodes | James S. Koford, Edwin R. Jones, Ranko Scepanovic, Michael D. Rostoker | 1999-10-05 |
| 5914887 | Congestion based cost factor computing apparatus for integrated circuit physical design automation system | Ranko Scepanovic, James S. Koford, Edwin Jones, Michael D. Rostoker | 1999-06-22 |
| 5903461 | Method of cell placement for an integrated circuit chip comprising chaotic placement and moving windows | Michael D. Rostoker, James S. Koford, Edwin R. Jones, Ranko Scepanovic | 1999-05-11 |
| 5875117 | Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system | Edwin R. Jones, James S. Koford, Ranko Scepanovic, Michael D. Rostoker | 1999-02-23 |
| 5870313 | Optimization processing for integrated circuit physical design automation system using parallel moving windows | James S. Koford, Ranko Scepanovic, Edwin R. Jones, Michael D. Rostoker | 1999-02-09 |
| 5864854 | System and method for maintaining a shared cache look-up table | — | 1999-01-26 |
| 5835378 | Computer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chip | Ranko Scepanovic, James S. Koford, Valeriy B. Kudryavtsev, Alexander E. Andreev, Stanislav V. Aleshin +1 more | 1998-11-10 |
| 5815403 | Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip | Edwin R. Jones, James S. Koford, Ranko Scepanovic, Michael D. Rostoker | 1998-09-29 |
| 5793644 | Cell placement alteration apparatus for integrated circuit chip physical design automation system | James S. Koford, Ranko Scepanovic, Edwin R. Jones, Michael D. Rostoker | 1998-08-11 |
| 5781439 | Method for producing integrated circuit chip having optimized cell placement | Michael D. Rostoker, James S. Koford, Edwin R. Jones, Ranko Scepanovic | 1998-07-14 |