Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10360341 | Integrated metal layer aware optimization of integrated circuit designs | David John Seibert, Pingkan Fok, Ramoji Karumuri Rao | 2019-07-23 |
| 6961916 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Feroze P. Taraporevala, Gary K. Yeap +4 more | 2005-11-01 |
| 6449756 | Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design | Sharad Malik, Lawrence Pileggi, Eric McCaughrin, Douglas B. Boyle | 2002-09-10 |
| 6442743 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Feroze P. Taraporevala, Gary K. Yeap +4 more | 2002-08-27 |
| 6367051 | System and method for concurrent buffer insertion and placement of logic gates | Lawrence Pileggi, Sharad Malik, Emre Tuncer, Satyamurthy Pullela, Altan Odabasioglu +1 more | 2002-04-02 |
| 6286128 | Method for design optimization using logical and physical information | Lawrence Pileggi, Majid Sarrafzadeh, Sharad Malik, Archie Li, Robert E. Shortt +17 more | 2001-09-04 |
| 6192508 | Method for logic optimization for improving timing and congestion during placement in integrated circuit design | Sharad Malik, Lawrence Pileggi, Gary K. Yeap, Douglas B. Boyle | 2001-02-20 |