Issued Patents All Time
Showing 26–33 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6775808 | Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuits | Salil Ravindra Raje, Dinesh D. Gaitonde, Olivier Coudert, Padmini Gopalakrishnan, Jackson David Kreiter | 2004-08-10 |
| 6651232 | Method and system for progressive clock tree or mesh construction concurrently with physical design | Christopher Dunn, Satyamurthy Pullela, Majid Sarrafzadeh, Tong Gao, Salil Ravindra Raje | 2003-11-18 |
| 6449756 | Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit design | Sharad Malik, Eric McCaughrin, Abhijeet Chakraborty, Douglas B. Boyle | 2002-09-10 |
| 6442743 | Placement method for integrated circuit design using topo-clustering | Majid Sarrafzadeh, Sharad Malik, Feroze P. Taraporevala, Abhijeet Chakraborty, Gary K. Yeap +4 more | 2002-08-27 |
| 6385760 | System and method for concurrent placement of gates and associated wiring | Majid Sarrafzadeh, Gary K. Yeap, Feroze P. Taraporevala, Tong Gao, Douglas B. Boyle | 2002-05-07 |
| 6367051 | System and method for concurrent buffer insertion and placement of logic gates | Sharad Malik, Emre Tuncer, Abhijeet Chakraborty, Satyamurthy Pullela, Altan Odabasioglu +1 more | 2002-04-02 |
| 6286128 | Method for design optimization using logical and physical information | Majid Sarrafzadeh, Sharad Malik, Abhijeet Chakraborty, Archie Li, Robert E. Shortt +17 more | 2001-09-04 |
| 6192508 | Method for logic optimization for improving timing and congestion during placement in integrated circuit design | Sharad Malik, Abhijeet Chakraborty, Gary K. Yeap, Douglas B. Boyle | 2001-02-20 |