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Hardware acceleration device handoff for using programmable integrated circuits as hardware accelerators |
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Creating a standard cell circuit design from a programmable logic device circuit design |
Dinesh D. Gaitonde |
2014-03-04 |
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Partitioning a large design across multiple devices |
David A. Knol, Abhishek Ranjan |
2011-01-18 |
| 7594212 |
Automatic pin placement for integrated circuits to aid circuit board design |
Dinesh D. Gaitonde |
2009-09-22 |
| 7519938 |
Strategies for generating an implementation of an electronic design |
Robert E. Shortt, David A. Knol |
2009-04-14 |
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Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices |
Abhishek Ranjan, David A. Knol |
2008-10-14 |
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System for representing the logical and physical information of an integrated circuit |
David A. Knol |
2008-08-26 |
| 7370302 |
Partitioning a large design across multiple devices |
David A. Knol, Abhishek Ranjan |
2008-05-06 |
| 7146595 |
Data structures for representing the logical and physical information of an integrated circuit |
David A. Knol |
2006-12-05 |
| 7120892 |
Process for adjusting data structures of a floorplan upon changes occurring |
David A. Knol |
2006-10-10 |
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System for creating a physical hierarchy of a chip without restriction by invading a logical hierarchy of logic blocks |
David A. Knol |
2006-10-03 |
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System for representing the logical and physical information of an integrated circuit |
David A. Knol |
2006-07-04 |
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Placement method for integrated circuit design using topo-clustering |
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Placement method for integrated circuit design using topo-clustering |
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2005-02-01 |
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Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuits |
Lawrence Pileggi, Dinesh D. Gaitonde, Olivier Coudert, Padmini Gopalakrishnan, Jackson David Kreiter |
2004-08-10 |
| 6651232 |
Method and system for progressive clock tree or mesh construction concurrently with physical design |
Lawrence Pileggi, Christopher Dunn, Satyamurthy Pullela, Majid Sarrafzadeh, Tong Gao |
2003-11-18 |
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Method to optimize net lists using simultaneous placement and logic optimization |
Padmini Gopalakrishnan |
2003-02-18 |
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Placement method for integrated circuit design using topo-clustering |
Majid Sarrafzadeh, Lawrence Pileggi, Sharad Malik, Feroze P. Taraporevala, Abhijeet Chakraborty +4 more |
2002-08-27 |
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Method for design optimization using logical and physical information |
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