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USPTO Patent Rankings Data through Dec 31, 2025
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David A. Knol — 19 Patents

AMD: 19 patents #585 of 9,280Top 7%
California: #31,067 of 386,348 inventorsTop 9%
Overall (All Time): #229,345 of 4,157,543Top 6%
19 Patents All Time
David A. Knol has been granted 19 US patents while listed as an inventor at AMD. The first was granted in 2006 and the most recent in January 2022. David A. Knol ranks #229,345 of 4,157,543 US inventors in our database (top 5.5%). Patent records list David A. Knol in معلمی نژاد, CA, US.

Issued Patents All Time

Showing 1–19 of 19 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11232219 Protection of electronic designs Bin Ochotta, Alec J. Wong, Nghia Do, Dennis McCrohan, Premduth Vidyanandan +1 more 2022-01-25 $118,965,000
9864828 Hardware acceleration device handoff for using programmable integrated circuits as hardware accelerators Susheel Puthana, Stephen P. Rozum, Sudipto Chakraborty, Yong Li, Fernando J. Martinez Vallina +6 more 2018-01-09 $17,814,000
9824173 Software development-based compilation flow for hardware implementation Bennet An, Henry E. Styles, Sonal Santan, Fernando J. Martinez Vallina, Pradip K. Jha +3 more 2017-11-21 $21,554,000
9679092 Constraint handling for parameterizable hardware description language Pradip K. Jha, Ravi N. Kurlagunda, Dinesh K. Monga, Stephen P. Rozum, Sudipto Chakraborty 2017-06-13 $18,200,000
9646118 Linking of simulators into a circuit design tool Rajvinder S. Klair, Sudipto Chakraborty 2017-05-09 $34,444,000
9465903 Programmable IC design creation using circuit board data Suman Kumar Timmireddy, Heera Nand, Awdhesh Kumar Sahu, Brendan M. O'Higgins, Siddharth Rele 2016-10-11 $26,856,000
8938704 Circuit module generation for programmable integrated circuits Siddharth Rele, Sumit Nagpal, Avdhesh Palliwal, Brendan M. O'Higgins 2015-01-20 $8,833,000
8839166 Method and apparatus for unified out-of-context flow and automation for IP reuse and hierarchical design flows Sudipto Chakraborty, Stephen P. Rozum, Ryan A. Linderman, Derrick S. Woods 2014-09-16 $9,620,000
8612916 System and method for import and export of design constraints Brendan M. O'Higgins, Pradip K. Jha, Dinesh K. Monga 2013-12-17 $9,305,000
8549454 System and method for automated configuration of design constraints Raymond Kong, Frederic Revenu, Dinesh K. Monga 2013-10-01 $7,574,000
7873927 Partitioning a large design across multiple devices Abhishek Ranjan, Salil Ravindra Raje 2011-01-18 $10,619,000
7519938 Strategies for generating an implementation of an electronic design Robert E. Shortt, Salil Ravindra Raje 2009-04-14 $6,987,000
7437695 Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices Abhishek Ranjan, Salil Ravindra Raje 2008-10-14 $5,631,000
7418686 System for representing the logical and physical information of an integrated circuit Salil Ravindra Raje 2008-08-26 $11,804,000
7370302 Partitioning a large design across multiple devices Abhishek Ranjan, Salil Ravindra Raje 2008-05-06 $7,758,000
7146595 Data structures for representing the logical and physical information of an integrated circuit Salil Ravindra Raje 2006-12-05 $10,249,000
7120892 Process for adjusting data structures of a floorplan upon changes occurring Salil Ravindra Raje 2006-10-10 $33,455,000
7117473 System for creating a physical hierarchy of a chip without restriction by invading a logical hierarchy of logic blocks Salil Ravindra Raje 2006-10-03 $7,381,000
7073149 System for representing the logical and physical information of an integrated circuit Salil Ravindra Raje 2006-07-04