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Software development-based compilation flow for hardware implementation |
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Constraint handling for parameterizable hardware description language |
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Programmable IC design creation using circuit board data |
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Circuit module generation for programmable integrated circuits |
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Method and apparatus for unified out-of-context flow and automation for IP reuse and hierarchical design flows |
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Partitioning a large design across multiple devices |
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Strategies for generating an implementation of an electronic design |
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2009-04-14 |
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Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices |
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2008-10-14 |
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System for representing the logical and physical information of an integrated circuit |
Salil Ravindra Raje |
2008-08-26 |
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Partitioning a large design across multiple devices |
Abhishek Ranjan, Salil Ravindra Raje |
2008-05-06 |
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Data structures for representing the logical and physical information of an integrated circuit |
Salil Ravindra Raje |
2006-12-05 |
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Process for adjusting data structures of a floorplan upon changes occurring |
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2006-10-10 |
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System for creating a physical hierarchy of a chip without restriction by invading a logical hierarchy of logic blocks |
Salil Ravindra Raje |
2006-10-03 |
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System for representing the logical and physical information of an integrated circuit |
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