Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11232219 | Protection of electronic designs | Bin Ochotta, Alec J. Wong, Nghia Do, Dennis McCrohan, Premduth Vidyanandan +1 more | 2022-01-25 |
| 9864828 | Hardware acceleration device handoff for using programmable integrated circuits as hardware accelerators | Susheel Puthana, Stephen P. Rozum, Sudipto Chakraborty, Yong Li, Fernando J. Martinez Vallina +6 more | 2018-01-09 |
| 9824173 | Software development-based compilation flow for hardware implementation | Bennet An, Henry E. Styles, Sonal Santan, Fernando J. Martinez Vallina, Pradip K. Jha +3 more | 2017-11-21 |
| 9679092 | Constraint handling for parameterizable hardware description language | Pradip K. Jha, Ravi N. Kurlagunda, Dinesh K. Monga, Stephen P. Rozum, Sudipto Chakraborty | 2017-06-13 |
| 9646118 | Linking of simulators into a circuit design tool | Rajvinder S. Klair, Sudipto Chakraborty | 2017-05-09 |
| 9465903 | Programmable IC design creation using circuit board data | Suman Kumar Timmireddy, Heera Nand, Awdhesh Kumar Sahu, Brendan M. O'Higgins, Siddharth Rele | 2016-10-11 |
| 8938704 | Circuit module generation for programmable integrated circuits | Siddharth Rele, Sumit Nagpal, Avdhesh Palliwal, Brendan M. O'Higgins | 2015-01-20 |
| 8839166 | Method and apparatus for unified out-of-context flow and automation for IP reuse and hierarchical design flows | Sudipto Chakraborty, Stephen P. Rozum, Ryan A. Linderman, Derrick S. Woods | 2014-09-16 |
| 8612916 | System and method for import and export of design constraints | Brendan M. O'Higgins, Pradip K. Jha, Dinesh K. Monga | 2013-12-17 |
| 8549454 | System and method for automated configuration of design constraints | Raymond Kong, Frederic Revenu, Dinesh K. Monga | 2013-10-01 |
| 7873927 | Partitioning a large design across multiple devices | Abhishek Ranjan, Salil Ravindra Raje | 2011-01-18 |
| 7519938 | Strategies for generating an implementation of an electronic design | Robert E. Shortt, Salil Ravindra Raje | 2009-04-14 |
| 7437695 | Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices | Abhishek Ranjan, Salil Ravindra Raje | 2008-10-14 |
| 7418686 | System for representing the logical and physical information of an integrated circuit | Salil Ravindra Raje | 2008-08-26 |
| 7370302 | Partitioning a large design across multiple devices | Abhishek Ranjan, Salil Ravindra Raje | 2008-05-06 |
| 7146595 | Data structures for representing the logical and physical information of an integrated circuit | Salil Ravindra Raje | 2006-12-05 |
| 7120892 | Process for adjusting data structures of a floorplan upon changes occurring | Salil Ravindra Raje | 2006-10-10 |
| 7117473 | System for creating a physical hierarchy of a chip without restriction by invading a logical hierarchy of logic blocks | Salil Ravindra Raje | 2006-10-03 |
| 7073149 | System for representing the logical and physical information of an integrated circuit | Salil Ravindra Raje | 2006-07-04 |