Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12271670 | Testbench for sub-design verification | Dhiraj Kumar Prasad, Saikat Bandyopadhyay, Ashish Jain, Shiyao Ge, Tapodyuti Mandal +1 more | 2025-04-08 |
| 11543452 | Hierarchical access simulation for signaling with more than two state values | Saikat Bandyopadhyay, Dhiraj Kumar Prasad, Ender Tunc Eroglu, Rupendra Bakoliya, Jayashree Rangarajan | 2023-01-03 |
| 11281834 | Protection of high-level language simulation models | Alec J. Wong, Sahil Goyal, Amit Kasat, Brian Cotter, Herve Alexanian | 2022-03-22 |
| 9646118 | Linking of simulators into a circuit design tool | David A. Knol, Sudipto Chakraborty | 2017-05-09 |