Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12271670 | Testbench for sub-design verification | Rajvinder S. Klair, Saikat Bandyopadhyay, Ashish Jain, Shiyao Ge, Tapodyuti Mandal +1 more | 2025-04-08 |
| 11543452 | Hierarchical access simulation for signaling with more than two state values | Saikat Bandyopadhyay, Rajvinder S. Klair, Ender Tunc Eroglu, Rupendra Bakoliya, Jayashree Rangarajan | 2023-01-03 |