Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12271670 | Testbench for sub-design verification | Rajvinder S. Klair, Dhiraj Kumar Prasad, Saikat Bandyopadhyay, Ashish Jain, Shiyao Ge +1 more | 2025-04-08 |
| 11475199 | Parallelizing simulation and hardware co-simulation of circuit designs through partitioning | Saikat Bandyopadhyay, Feng Cai, Vinayak Thonda, Sree Rohith Pulipaka | 2022-10-18 |
| 11055458 | Functional coverage of designs using transition bins and cross coverage | Aparna Suresh, Vinayak Thonda | 2021-07-06 |