Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12271670 | Testbench for sub-design verification | Rajvinder S. Klair, Dhiraj Kumar Prasad, Ashish Jain, Shiyao Ge, Tapodyuti Mandal +1 more | 2025-04-08 |
| 11543452 | Hierarchical access simulation for signaling with more than two state values | Rajvinder S. Klair, Dhiraj Kumar Prasad, Ender Tunc Eroglu, Rupendra Bakoliya, Jayashree Rangarajan | 2023-01-03 |
| 11475199 | Parallelizing simulation and hardware co-simulation of circuit designs through partitioning | Feng Cai, Tapodyuti Mandal, Vinayak Thonda, Sree Rohith Pulipaka | 2022-10-18 |
| 11443088 | Simulation using accelerated models | Gaurav Verma | 2022-09-13 |
| 11003818 | Range computation of bitwise operators | Ashish Jain, Jason Villarreal | 2021-05-11 |
| 10726182 | Operator aware finite state machine for circuit design simulation | Sandeep S. Deshpande, Feng Cai | 2020-07-28 |
| 10671785 | Framework for reusing cores in simulation | Valeria Mihalache, Kumar Deepak, Sandeep S. Deshpande, Feng Cai | 2020-06-02 |
| 10437949 | Scheduling events in hardware design language simulation | Valeria Mihalache, Kumar Deepak | 2019-10-08 |
| 10296673 | Mixed-language simulation | Ishita Ghosh, Hem C. Neema, Jason Villarreal, Kumar Deepak | 2019-05-21 |
| 9582619 | Simulation of a circuit design block using pattern matching | David K. Liddell, Feng Cai | 2017-02-28 |
| 9223910 | Performance and memory efficient modeling of HDL ports for simulation | Ishita Ghosh, Kumar Deepak, Hem C. Neema, David K. Liddell | 2015-12-29 |