Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10671785 | Framework for reusing cores in simulation | Kumar Deepak, Saikat Bandyopadhyay, Sandeep S. Deshpande, Feng Cai | 2020-06-02 |
| 10437949 | Scheduling events in hardware design language simulation | Kumar Deepak, Saikat Bandyopadhyay | 2019-10-08 |
| 9619601 | Control and data flow graph generation for hardware description languages | Jason Villarreal | 2017-04-11 |
| 9135384 | Compilation and simulation of a circuit design | Sonal Santan, Hem C. Neema | 2015-09-15 |
| 8838431 | Mixed-language simulation | Hem C. Neema, Kumar Deepak, Sonal Santan | 2014-09-16 |
| 8768678 | Scheduling processes in simulation of a circuit design based on simulation costs and runtime states of HDL processes | Christopher H. Kingsley, Jimmy Zhenming Wang, Kumar Deepak | 2014-07-01 |
| 8516413 | Compilation and simulation of a circuit design | Sandeep S. Deshpande, Hem C. Neema, Kumar Deepak, Sonal Santan, David K. Liddell | 2013-08-20 |
| 8495539 | Scheduling processes in simulation of a circuit design | Kumar Deepak, Hem C. Neema, Sonal Santan | 2013-07-23 |