Lucio Lanza — 11 Patents at Efabless

Lucio Lanza has been granted 11 US patents while listed as an inventor at Efabless. The first was granted in 2007 and the most recent in October 2023. Lucio Lanza ranks #435,149 of 4,157,543 US inventors in our database (top 10.5%). Patent records list Lucio Lanza in Palo Alto, CA, US.

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Showing 1–11 of 11 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
11775722	Systems and methods for obfuscating a circuit design	Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more	2023-10-03
11748541	Methods for engineering integrated circuit design and development	Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more	2023-09-05
11301609	Systems and methods for obfuscating a circuit design	Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more	2022-04-12
11182526	Methods for engineering integrated circuit design and development	Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more	2021-11-23
10671700	Systems and methods for obfuscating a circuit design	Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more	2020-06-02
10452802	Methods for engineering integrated circuit design and development	Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more	2019-10-22
10437953	Systems for engineering integrated circuit design and development	Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more	2019-10-08
10423748	Systems and methods for obfuscating a circuit design	Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more	2019-09-24
7906254	Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features	Lawrence Pileggi, Andrzej Strojwas	2011-03-15	$1,721,000
7278118	Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features	Lawrence Pileggi, Andrzej Strojwas	2007-10-02	$3,189,000
7191413	Method and apparatus for thermal testing of semiconductor chip designs	Rajit Chandra	2007-03-13

Lucio Lanza — 11 Patents

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