Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11775722 | Systems and methods for obfuscating a circuit design | Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more | 2023-10-03 |
| 11748541 | Methods for engineering integrated circuit design and development | Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more | 2023-09-05 |
| 11301609 | Systems and methods for obfuscating a circuit design | Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more | 2022-04-12 |
| 11182526 | Methods for engineering integrated circuit design and development | Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more | 2021-11-23 |
| 10671700 | Systems and methods for obfuscating a circuit design | Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more | 2020-06-02 |
| 10452802 | Methods for engineering integrated circuit design and development | Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more | 2019-10-22 |
| 10437953 | Systems for engineering integrated circuit design and development | Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more | 2019-10-08 |
| 10423748 | Systems and methods for obfuscating a circuit design | Bertrand Irissou, John M. Hughes, Mohamed K. Kassem, Michael S. Wishart, Rajeev Srivastava +4 more | 2019-09-24 |
| 7906254 | Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features | Lawrence Pileggi, Andrzej Strojwas | 2011-03-15 |
| 7278118 | Method and process for design of integrated circuits using regular geometry patterns to obtain geometrically consistent component features | Lawrence Pileggi, Andrzej Strojwas | 2007-10-02 |
| 7191413 | Method and apparatus for thermal testing of semiconductor chip designs | Rajit Chandra | 2007-03-13 |