Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10678983 | Local retiming optimization for circuit designs | Chaithanya Dudha, Bing Tian, Ashish Sirasao | 2020-06-09 |
| 10664561 | Automatic pipelining of memory circuits | Pradip Kar, Satyaprakash Pareek, Bing Tian | 2020-05-26 |
| 10606979 | Verifying equivalence of design latency | Bing Tian, Chaithanya Dudha | 2020-03-31 |
| 10303833 | Parallelizing timing-based operations for circuit designs | Aman Gayasen, Surya Pratik Saha, Elliott Delaye, Ashish Sirasao | 2019-05-28 |
| 10289786 | Circuit design transformation for automatic latency reduction | Chaithanya Dudha, Ashish Sirasao, Nithin Kumar Guggilla | 2019-05-14 |
| 7831856 | Detection of timing errors in programmable logic devices | Liren Liu, Jianshe He | 2010-11-09 |